DE69803335D1 - Herstellung von sub-lithographischen Strukturen - Google Patents
Herstellung von sub-lithographischen StrukturenInfo
- Publication number
- DE69803335D1 DE69803335D1 DE69803335T DE69803335T DE69803335D1 DE 69803335 D1 DE69803335 D1 DE 69803335D1 DE 69803335 T DE69803335 T DE 69803335T DE 69803335 T DE69803335 T DE 69803335T DE 69803335 D1 DE69803335 D1 DE 69803335D1
- Authority
- DE
- Germany
- Prior art keywords
- sub
- manufacture
- lithographic structures
- lithographic
- structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/884,732 US6051497A (en) | 1997-06-30 | 1997-06-30 | Formation of sub-groundrule features |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69803335D1 true DE69803335D1 (de) | 2002-02-28 |
DE69803335T2 DE69803335T2 (de) | 2002-09-19 |
Family
ID=25385267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69803335T Expired - Lifetime DE69803335T2 (de) | 1997-06-30 | 1998-05-29 | Herstellung von sub-lithographischen Strukturen |
Country Status (8)
Country | Link |
---|---|
US (1) | US6051497A (de) |
EP (1) | EP0889516B1 (de) |
JP (1) | JPH1174273A (de) |
KR (1) | KR100536051B1 (de) |
CN (1) | CN1121718C (de) |
DE (1) | DE69803335T2 (de) |
HK (1) | HK1015544A1 (de) |
TW (1) | TW405200B (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6740573B2 (en) * | 1995-02-17 | 2004-05-25 | Micron Technology, Inc. | Method for forming an integrated circuit interconnect using a dual poly process |
US6162731A (en) * | 1999-06-08 | 2000-12-19 | United Silicon Incorporated | Method of defining a conductive layer |
KR100393945B1 (ko) * | 2001-02-24 | 2003-08-06 | 이노스텍 (주) | 금속 박막 저항체 소자의 제조 방법 및 이를 이용한 금속 박막 온도 센서의 제조 방법 |
TW559950B (en) * | 2002-03-13 | 2003-11-01 | Macronix Int Co Ltd | Memory device and method of forming passivation film thereof |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5651855A (en) * | 1992-07-28 | 1997-07-29 | Micron Technology, Inc. | Method of making self aligned contacts to silicon substrates during the manufacture of integrated circuits |
US5328553A (en) * | 1993-02-02 | 1994-07-12 | Motorola Inc. | Method for fabricating a semiconductor device having a planar surface |
US5490634A (en) * | 1993-02-10 | 1996-02-13 | Michigan Biotechnology Institute | Biological method for coal comminution |
US5494857A (en) * | 1993-07-28 | 1996-02-27 | Digital Equipment Corporation | Chemical mechanical planarization of shallow trenches in semiconductor substrates |
US5661053A (en) * | 1994-05-25 | 1997-08-26 | Sandisk Corporation | Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
US5506172A (en) * | 1994-08-29 | 1996-04-09 | Micron Technology, Inc. | Semiconductor processing method of forming an electrical interconnection between an outer layer and an inner layer |
JP3413697B2 (ja) * | 1995-11-17 | 2003-06-03 | ソニー株式会社 | 配線形成方法 |
US5639692A (en) * | 1996-04-08 | 1997-06-17 | Chartered Semiconductor Manufacturing Pte, Ltd. | Non-etch back SOG process using a metal via stud |
JPH1010716A (ja) * | 1996-06-19 | 1998-01-16 | Brother Ind Ltd | 感光記録媒体及びそれを使用する画像形成装置 |
JPH10107161A (ja) * | 1996-09-27 | 1998-04-24 | Sony Corp | 半導体装置及びその製造方法 |
-
1997
- 1997-06-30 US US08/884,732 patent/US6051497A/en not_active Expired - Lifetime
-
1998
- 1998-05-29 EP EP98109829A patent/EP0889516B1/de not_active Expired - Lifetime
- 1998-05-29 DE DE69803335T patent/DE69803335T2/de not_active Expired - Lifetime
- 1998-06-24 TW TW087110162A patent/TW405200B/zh not_active IP Right Cessation
- 1998-06-26 JP JP10180590A patent/JPH1174273A/ja active Pending
- 1998-06-29 KR KR1019980024785A patent/KR100536051B1/ko not_active IP Right Cessation
- 1998-06-30 CN CN98115620A patent/CN1121718C/zh not_active Expired - Fee Related
-
1999
- 1999-02-11 HK HK99100572A patent/HK1015544A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US6051497A (en) | 2000-04-18 |
JPH1174273A (ja) | 1999-03-16 |
KR19990007420A (ko) | 1999-01-25 |
KR100536051B1 (ko) | 2006-02-28 |
EP0889516B1 (de) | 2002-01-02 |
EP0889516A3 (de) | 1999-10-13 |
TW405200B (en) | 2000-09-11 |
CN1121718C (zh) | 2003-09-17 |
HK1015544A1 (en) | 1999-10-15 |
CN1204151A (zh) | 1999-01-06 |
EP0889516A2 (de) | 1999-01-07 |
DE69803335T2 (de) | 2002-09-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE |