DE69727939D1 - RAM memory cell with low power consumption and a single bit line - Google Patents

RAM memory cell with low power consumption and a single bit line

Info

Publication number
DE69727939D1
DE69727939D1 DE69727939T DE69727939T DE69727939D1 DE 69727939 D1 DE69727939 D1 DE 69727939D1 DE 69727939 T DE69727939 T DE 69727939T DE 69727939 T DE69727939 T DE 69727939T DE 69727939 D1 DE69727939 D1 DE 69727939D1
Authority
DE
Germany
Prior art keywords
memory cell
power consumption
bit line
low power
single bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69727939T
Other languages
German (de)
Inventor
Danilo Rimondi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69727939D1 publication Critical patent/DE69727939D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE69727939T 1997-11-28 1997-11-28 RAM memory cell with low power consumption and a single bit line Expired - Lifetime DE69727939D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97120944A EP0920027B1 (en) 1997-11-28 1997-11-28 A low power RAM memory cell with a single bit line

Publications (1)

Publication Number Publication Date
DE69727939D1 true DE69727939D1 (en) 2004-04-08

Family

ID=8227705

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69727939T Expired - Lifetime DE69727939D1 (en) 1997-11-28 1997-11-28 RAM memory cell with low power consumption and a single bit line

Country Status (3)

Country Link
US (3) US6212094B1 (en)
EP (1) EP0920027B1 (en)
DE (1) DE69727939D1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2808114B1 (en) * 1999-07-09 2002-07-12 Suisse Electronique Microtech RAM MEMORY
CA2299991A1 (en) * 2000-03-03 2001-09-03 Mosaid Technologies Incorporated A memory cell for embedded memories
US6580657B2 (en) * 2001-01-04 2003-06-17 International Business Machines Corporation Low-power organic light emitting diode pixel circuit
GB2384092A (en) * 2002-01-14 2003-07-16 Zarlink Semiconductor Ab Low power static random access memory
US10201760B2 (en) * 2002-12-10 2019-02-12 Sony Interactive Entertainment America Llc System and method for compressing video based on detected intraframe motion
US6804143B1 (en) 2003-04-02 2004-10-12 Cogent Chipware Inc. Write-assisted SRAM bit cell
US7042776B2 (en) * 2004-02-18 2006-05-09 International Business Machines Corporation Method and circuit for dynamic read margin control of a memory array
JP4287768B2 (en) * 2004-03-16 2009-07-01 パナソニック株式会社 Semiconductor memory device
US7307873B2 (en) * 2006-02-21 2007-12-11 M2000 Sa. Memory with five-transistor bit cells and associated control circuit
US7440312B2 (en) * 2006-10-02 2008-10-21 Analog Devices, Inc. Memory write timing system
US7440313B2 (en) * 2006-11-17 2008-10-21 Freescale Semiconductor, Inc. Two-port SRAM having improved write operation
US7609541B2 (en) * 2006-12-27 2009-10-27 Freescale Semiconductor, Inc. Memory cells with lower power consumption during a write operation
US7957178B2 (en) * 2008-01-04 2011-06-07 Texas Instruments Incorporated Storage cell having buffer circuit for driving the bitline
US8593861B2 (en) 2011-10-10 2013-11-26 International Business Machines Corporation Asymmetric memory cells
CN103873495B (en) * 2012-12-10 2019-01-15 联想(北京)有限公司 The method of file synchronization and the electronic equipment for using this method
WO2015102569A2 (en) * 2013-12-30 2015-07-09 The Regents Of The University Of Michigan Static random access memory cell having improved write margin for use in ultra-low power application
US9171586B2 (en) 2014-02-14 2015-10-27 Oracle International Corporation Dual memory bitcell with shared virtual ground

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6126997A (en) * 1984-07-18 1986-02-06 Toshiba Corp Semiconductor memory device
JPH0834059B2 (en) * 1990-08-31 1996-03-29 三菱電機株式会社 Semiconductor memory device
JP3230848B2 (en) * 1991-09-20 2001-11-19 三菱電機株式会社 Static random access memory device
JPH06103781A (en) * 1992-09-21 1994-04-15 Sharp Corp Memory cell circuit
EP0718847B1 (en) * 1994-12-22 2003-06-25 Cypress Semiconductor Corporation Single ended dual port memory cell
US5894434A (en) * 1995-12-22 1999-04-13 Texas Instruments Incorporated MOS static memory array
JP2944538B2 (en) * 1996-10-24 1999-09-06 日本電気アイシーマイコンシステム株式会社 Semiconductor memory circuit
US5831896A (en) * 1996-12-17 1998-11-03 International Business Machines Corporation Memory cell
US6011711A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. SRAM cell with p-channel pull-up sources connected to bit lines
US5808933A (en) * 1997-03-28 1998-09-15 International Business Machines Corporation Zero-write-cycle memory cell apparatus
JPH1139877A (en) * 1997-07-15 1999-02-12 Mitsubishi Electric Corp Semiconductor storage device
US5986923A (en) * 1998-05-06 1999-11-16 Hewlett-Packard Company Method and apparatus for improving read/write stability of a single-port SRAM cell

Also Published As

Publication number Publication date
US20010006475A1 (en) 2001-07-05
EP0920027A1 (en) 1999-06-02
US6459611B2 (en) 2002-10-01
US20030026150A1 (en) 2003-02-06
US6212094B1 (en) 2001-04-03
EP0920027B1 (en) 2004-03-03

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Legal Events

Date Code Title Description
8332 No legal effect for de