DE69709885D1 - Speichersystem und einrichtung - Google Patents
Speichersystem und einrichtungInfo
- Publication number
- DE69709885D1 DE69709885D1 DE69709885T DE69709885T DE69709885D1 DE 69709885 D1 DE69709885 D1 DE 69709885D1 DE 69709885 T DE69709885 T DE 69709885T DE 69709885 T DE69709885 T DE 69709885T DE 69709885 D1 DE69709885 D1 DE 69709885D1
- Authority
- DE
- Germany
- Prior art keywords
- furnishing
- storage system
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/729,261 US5892981A (en) | 1996-10-10 | 1996-10-10 | Memory system and device |
PCT/US1997/018128 WO1998015897A1 (en) | 1996-10-10 | 1997-10-06 | Memory system and device |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69709885D1 true DE69709885D1 (de) | 2002-02-28 |
DE69709885T2 DE69709885T2 (de) | 2002-06-27 |
Family
ID=24930266
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69709885T Expired - Fee Related DE69709885T2 (de) | 1996-10-10 | 1997-10-06 | Speichersystem und einrichtung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5892981A (de) |
EP (1) | EP0931291B1 (de) |
JP (1) | JP3860842B2 (de) |
DE (1) | DE69709885T2 (de) |
WO (1) | WO1998015897A1 (de) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6173345B1 (en) * | 1998-11-03 | 2001-01-09 | Intel Corporation | Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem |
US6391483B1 (en) | 1999-03-30 | 2002-05-21 | Carnegie Mellon University | Magnetic device and method of forming same |
US7051130B1 (en) | 1999-10-19 | 2006-05-23 | Rambus Inc. | Integrated circuit device that stores a value representative of a drive strength setting |
US6321282B1 (en) | 1999-10-19 | 2001-11-20 | Rambus Inc. | Apparatus and method for topography dependent signaling |
US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
KR100389916B1 (ko) * | 2000-08-28 | 2003-07-04 | 삼성전자주식회사 | 메모리 모듈 및 메모리 컨트롤러 |
US7079775B2 (en) * | 2001-02-05 | 2006-07-18 | Finisar Corporation | Integrated memory mapped controller circuit for fiber optics transceiver |
US6658523B2 (en) * | 2001-03-13 | 2003-12-02 | Micron Technology, Inc. | System latency levelization for read data |
US6675272B2 (en) | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
EP1291778B1 (de) * | 2001-04-24 | 2007-06-27 | Rambus Inc. | Verfahren und Gerät zum Koordinieren von Speicheroperationen zwischen unterschiedlich angeordneten Speicherkomponenten |
US8391039B2 (en) * | 2001-04-24 | 2013-03-05 | Rambus Inc. | Memory module with termination component |
US6622222B2 (en) * | 2001-04-26 | 2003-09-16 | International Business Machines Corporation | Sequencing data on a shared data bus via a memory buffer to prevent data overlap during multiple memory read operations |
DE10123769C1 (de) * | 2001-05-16 | 2002-12-12 | Infineon Technologies Ag | Verfahren zur Anpassung unterschiedlicher Signallaufzeiten zwischen einer Steuerung und wenigstens zweier Verarbeitungseinheiten sowie Rechnersystem |
DE60237301D1 (de) | 2001-10-22 | 2010-09-23 | Rambus Inc | Phaseneinstellvorrichtung und verfahren für ein speicherbaustein-signalisierungssystem |
US7609778B2 (en) * | 2001-12-20 | 2009-10-27 | Richard S. Norman | Methods, apparatus, and systems for reducing interference on nearby conductors |
US6703868B2 (en) | 2001-12-20 | 2004-03-09 | Hyperchip Inc. | Methods, apparatus, and systems for reducing interference on nearby conductors |
US20030117183A1 (en) * | 2001-12-20 | 2003-06-26 | Claude Thibeault | Methods, apparatus, and systems for reducing interference on nearby conductors |
US6897497B2 (en) * | 2001-12-20 | 2005-05-24 | Hyperchip Inc. | Methods, apparatus, and systems for reducing interference on nearby conductors |
US6944040B1 (en) | 2001-12-28 | 2005-09-13 | Netlogic Microsystems, Inc. | Programmable delay circuit within a content addressable memory |
US6650575B1 (en) * | 2001-12-28 | 2003-11-18 | Netlogic Microsystems, Inc. | Programmable delay circuit within a content addressable memory |
US7135903B2 (en) * | 2002-09-03 | 2006-11-14 | Rambus Inc. | Phase jumping locked loop circuit |
US6922091B2 (en) | 2002-09-03 | 2005-07-26 | Rambus Inc. | Locked loop circuit with clock hold function |
US6759881B2 (en) * | 2002-03-22 | 2004-07-06 | Rambus Inc. | System with phase jumping locked loop circuit |
US6911853B2 (en) * | 2002-03-22 | 2005-06-28 | Rambus Inc. | Locked loop with dual rail regulation |
US6952123B2 (en) | 2002-03-22 | 2005-10-04 | Rambus Inc. | System with dual rail regulated locked loop |
JP3835328B2 (ja) * | 2002-03-27 | 2006-10-18 | ブラザー工業株式会社 | メモリ制御装置 |
US6956257B2 (en) | 2002-11-18 | 2005-10-18 | Carnegie Mellon University | Magnetic memory element and memory device including same |
US7685188B2 (en) * | 2004-01-23 | 2010-03-23 | Microsoft Corporation | Automated generation of computer-executable compensation procedures for previously executed methods |
US7669027B2 (en) | 2004-08-19 | 2010-02-23 | Micron Technology, Inc. | Memory command delay balancing in a daisy-chained memory topology |
US7301831B2 (en) | 2004-09-15 | 2007-11-27 | Rambus Inc. | Memory systems with variable delays for write data signals |
US7280428B2 (en) | 2004-09-30 | 2007-10-09 | Rambus Inc. | Multi-column addressing mode memory system including an integrated circuit memory device |
US8595459B2 (en) * | 2004-11-29 | 2013-11-26 | Rambus Inc. | Micro-threaded memory |
US8065457B2 (en) * | 2005-09-09 | 2011-11-22 | Advanced Micro Devices, Inc. | Delayed memory access request arbitration |
DE102006062725B4 (de) * | 2006-04-15 | 2018-01-18 | Polaris Innovations Ltd. | Speichersystem mit integrierten Speicherbausteinen sowie Verfahren zum Betrieb eines Speichersystems |
US20070260841A1 (en) | 2006-05-02 | 2007-11-08 | Hampel Craig E | Memory module with reduced access granularity |
US20080114960A1 (en) * | 2006-11-14 | 2008-05-15 | Tau-Li Huang | Memory control methods for accessing a memory with partial or full serial transmission, and related apparatus |
EP3200189B1 (de) | 2007-04-12 | 2021-06-02 | Rambus Inc. | Speichersystem mit punkt-zu-punkt-anforderungsverbindung |
US8438356B2 (en) * | 2007-10-01 | 2013-05-07 | Marvell World Trade Ltd. | Flash memory controller |
US8799606B2 (en) * | 2007-12-20 | 2014-08-05 | International Business Machines Corporation | Computer memory subsystem for enhancing signal quality |
JP2011081732A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体装置及びその調整方法並びにデータ処理システム |
US9330034B2 (en) * | 2010-04-14 | 2016-05-03 | Rambus Inc. | Levelization of memory interface for communicating with multiple memory devices |
US9268719B2 (en) | 2011-08-05 | 2016-02-23 | Rambus Inc. | Memory signal buffers and modules supporting variable access granularity |
US9336112B2 (en) | 2012-06-19 | 2016-05-10 | Apple Inc. | Parallel status polling of multiple memory devices |
JP2022056144A (ja) | 2020-09-29 | 2022-04-08 | 富士フイルムビジネスイノベーション株式会社 | プログラマブル論理回路、情報処理装置、情報処理システム、及びプログラム |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1158739A (en) * | 1980-04-30 | 1983-12-13 | William Rodman | Distributed network synchronization system |
US4604717A (en) * | 1983-02-18 | 1986-08-05 | Rca Corporation | Method and apparatus for measuring the time delay between signals |
EP0238090B1 (de) * | 1986-03-20 | 1997-02-05 | Nec Corporation | Mikrorechner mit Zugriffsfähigkeit auf einen internen Speicher mit gewünschter variabler Zugriffszeit |
JPS6315354A (ja) * | 1986-07-07 | 1988-01-22 | Hitachi Ltd | 分散システムにおけるタイマ一致化管理方式 |
US5237674A (en) * | 1987-04-11 | 1993-08-17 | Apple Computer, Inc. | Self identifying scheme for memory module including circuitry for identfying accessing speed |
CA1301261C (en) * | 1988-04-27 | 1992-05-19 | Wayne D. Grover | Method and apparatus for clock distribution and for distributed clock synchronization |
JPH0212541A (ja) * | 1988-04-29 | 1990-01-17 | Internatl Business Mach Corp <Ibm> | コンピユーテイング・システム及びその動作方法 |
US5189246A (en) * | 1989-09-28 | 1993-02-23 | Csir | Timing apparatus |
US4998262A (en) * | 1989-10-10 | 1991-03-05 | Hewlett-Packard Company | Generation of topology independent reference signals |
US5359722A (en) * | 1990-07-23 | 1994-10-25 | International Business Machines Corporation | Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM |
JP2993239B2 (ja) * | 1991-11-28 | 1999-12-20 | 株式会社日立製作所 | 階層間ディレイ配分方法 |
US5509138A (en) * | 1993-03-22 | 1996-04-16 | Compaq Computer Corporation | Method for determining speeds of memory modules |
JPH0713905A (ja) * | 1993-06-23 | 1995-01-17 | Hitachi Ltd | 記憶装置システム及びその制御方法 |
US5408506A (en) * | 1993-07-09 | 1995-04-18 | Apple Computer, Inc. | Distributed time synchronization system and method |
JPH08123717A (ja) * | 1994-10-25 | 1996-05-17 | Oki Electric Ind Co Ltd | 半導体記憶装置 |
-
1996
- 1996-10-10 US US08/729,261 patent/US5892981A/en not_active Expired - Fee Related
-
1997
- 1997-10-06 WO PCT/US1997/018128 patent/WO1998015897A1/en active IP Right Grant
- 1997-10-06 EP EP97910834A patent/EP0931291B1/de not_active Expired - Lifetime
- 1997-10-06 JP JP51769398A patent/JP3860842B2/ja not_active Expired - Fee Related
- 1997-10-06 DE DE69709885T patent/DE69709885T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69709885T2 (de) | 2002-06-27 |
EP0931291B1 (de) | 2002-01-02 |
WO1998015897A1 (en) | 1998-04-16 |
JP2001505684A (ja) | 2001-04-24 |
EP0931291A1 (de) | 1999-07-28 |
JP3860842B2 (ja) | 2006-12-20 |
US5892981A (en) | 1999-04-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US |
|
8339 | Ceased/non-payment of the annual fee |