DE69637074D1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung

Info

Publication number
DE69637074D1
DE69637074D1 DE69637074T DE69637074T DE69637074D1 DE 69637074 D1 DE69637074 D1 DE 69637074D1 DE 69637074 T DE69637074 T DE 69637074T DE 69637074 T DE69637074 T DE 69637074T DE 69637074 D1 DE69637074 D1 DE 69637074D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69637074T
Other languages
English (en)
Other versions
DE69637074T2 (de
Inventor
Yasuhiro Hotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69637074D1 publication Critical patent/DE69637074D1/de
Application granted granted Critical
Publication of DE69637074T2 publication Critical patent/DE69637074T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
DE69637074T 1996-02-22 1996-06-20 Halbleiterspeicheranordnung Expired - Lifetime DE69637074T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3529496A JP3219236B2 (ja) 1996-02-22 1996-02-22 半導体記憶装置
JP3529496 1996-02-22

Publications (2)

Publication Number Publication Date
DE69637074D1 true DE69637074D1 (de) 2007-06-21
DE69637074T2 DE69637074T2 (de) 2008-01-10

Family

ID=12437763

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69637074T Expired - Lifetime DE69637074T2 (de) 1996-02-22 1996-06-20 Halbleiterspeicheranordnung

Country Status (6)

Country Link
US (1) US5717637A (de)
EP (1) EP0791931B1 (de)
JP (1) JP3219236B2 (de)
KR (1) KR100195671B1 (de)
DE (1) DE69637074T2 (de)
TW (1) TW400525B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6677995B1 (en) * 1999-02-04 2004-01-13 Agere Systems Inc. Array readout system
US6430099B1 (en) 2001-05-11 2002-08-06 Broadcom Corporation Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation
US6906962B2 (en) * 2002-09-30 2005-06-14 Agere Systems Inc. Method for defining the initial state of static random access memory
US9177671B2 (en) * 2012-02-23 2015-11-03 Apple Inc. Memory with bit line capacitive loading

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2534733B2 (ja) * 1987-10-09 1996-09-18 日本電気株式会社 不揮発性半導体記憶装置
US5257235A (en) * 1989-04-25 1993-10-26 Kabushiki Kaisha Toshiba Semiconductor memory device having serial access mode
JP2680936B2 (ja) * 1991-02-13 1997-11-19 シャープ株式会社 半導体記憶装置
JP2723695B2 (ja) * 1991-07-02 1998-03-09 シャープ株式会社 半導体記憶装置
US5455802A (en) * 1992-12-22 1995-10-03 Sgs-Thomson Microelectronics, Inc. Dual dynamic sense amplifiers for a memory array
JP3176228B2 (ja) * 1994-08-23 2001-06-11 シャープ株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JP3219236B2 (ja) 2001-10-15
TW400525B (en) 2000-08-01
US5717637A (en) 1998-02-10
JPH09231762A (ja) 1997-09-05
EP0791931A3 (de) 2003-07-23
EP0791931A2 (de) 1997-08-27
EP0791931B1 (de) 2007-05-09
KR100195671B1 (ko) 1999-06-15
DE69637074T2 (de) 2008-01-10
KR970063268A (ko) 1997-09-12

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