DE69515189T2 - SOI-Substrat und Verfahren zur Herstellung - Google Patents

SOI-Substrat und Verfahren zur Herstellung

Info

Publication number
DE69515189T2
DE69515189T2 DE69515189T DE69515189T DE69515189T2 DE 69515189 T2 DE69515189 T2 DE 69515189T2 DE 69515189 T DE69515189 T DE 69515189T DE 69515189 T DE69515189 T DE 69515189T DE 69515189 T2 DE69515189 T2 DE 69515189T2
Authority
DE
Germany
Prior art keywords
manufacturing
soi substrate
soi
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69515189T
Other languages
English (en)
Other versions
DE69515189D1 (de
Inventor
Sadao Nakashima
Katsutoshi Izumi
Norihiko Ohwada
Tatsuhiko Katayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Techxiv Corp
NTT Electronics Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NTT Electronics Corp
Nippon Telegraph and Telephone Corp
Komatsu Electronic Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NTT Electronics Corp, Nippon Telegraph and Telephone Corp, Komatsu Electronic Metals Co Ltd filed Critical NTT Electronics Corp
Publication of DE69515189D1 publication Critical patent/DE69515189D1/de
Application granted granted Critical
Publication of DE69515189T2 publication Critical patent/DE69515189T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
DE69515189T 1994-03-23 1995-03-17 SOI-Substrat und Verfahren zur Herstellung Expired - Lifetime DE69515189T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6076538A JP3036619B2 (ja) 1994-03-23 1994-03-23 Ｓｏｉ基板の製造方法およびｓｏｉ基板

Publications (2)

Publication Number Publication Date
DE69515189D1 DE69515189D1 (de) 2000-04-06
DE69515189T2 true DE69515189T2 (de) 2000-11-23

Family

ID=13608053

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69515189T Expired - Lifetime DE69515189T2 (de) 1994-03-23 1995-03-17 SOI-Substrat und Verfahren zur Herstellung

Country Status (8)

Country Link
US (2) US5658809A (de)
EP (1) EP0675534B1 (de)
JP (1) JP3036619B2 (de)
KR (1) KR0145824B1 (de)
CZ (1) CZ281798B6 (de)
DE (1) DE69515189T2 (de)
FI (1) FI951340A (de)
TW (1) TW401609B (de)

Families Citing this family (70)

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JP3036619B2 (ja) * 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
JP3427114B2 (ja) * 1994-06-03 2003-07-14 コマツ電子金属株式会社 半導体デバイス製造方法
JP3204855B2 (ja) * 1994-09-30 2001-09-04 新日本製鐵株式会社 半導体基板の製造方法
US5989981A (en) * 1996-07-05 1999-11-23 Nippon Telegraph And Telephone Corporation Method of manufacturing SOI substrate
JPH10223551A (ja) * 1997-02-12 1998-08-21 Nec Corp Ｓｏｉ基板の製造方法
JPH10284431A (ja) * 1997-04-11 1998-10-23 Sharp Corp Ｓｏｉ基板の製造方法
KR20010013993A (ko) * 1997-06-19 2001-02-26 야마모토 카즈모토 Ｓｏｉ 기판과 그 제조 방법, 및 반도체 디바이스와 그제조 방법
JPH1126390A (ja) * 1997-07-07 1999-01-29 Kobe Steel Ltd 欠陥発生防止方法
JPH1197377A (ja) * 1997-09-24 1999-04-09 Nec Corp Ｓｏｉ基板の製造方法
JPH11168106A (ja) * 1997-09-30 1999-06-22 Fujitsu Ltd 半導体基板の処理方法
KR100258096B1 (ko) * 1997-12-01 2000-06-01 정선종 에스오아이(soi) 기판 제조방법
KR100565438B1 (ko) * 1998-02-02 2006-03-30 신닛뽄세이테쯔 카부시키카이샤 Soi기판 및 그의 제조방법
US6117711A (en) * 1998-03-02 2000-09-12 Texas Instruments - Acer Incorporated Method of making single-electron-tunneling CMOS transistors
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP3762144B2 (ja) 1998-06-18 2006-04-05 キヤノン株式会社 Ｓｏｉ基板の作製方法
KR100292818B1 (ko) * 1998-07-02 2001-11-05 윤종용 모오스트랜지스터제조방법
JP2000082679A (ja) * 1998-07-08 2000-03-21 Canon Inc 半導体基板とその作製方法
JP2003289051A (ja) * 1998-09-10 2003-10-10 Nippon Steel Corp Ｓｉｍｏｘ基板およびその製造方法
US6753229B1 (en) 1998-12-04 2004-06-22 The Regents Of The University Of California Multiple-thickness gate oxide formed by oxygen implantation
JP3911901B2 (ja) 1999-04-09 2007-05-09 信越半導体株式会社 Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法
US6362075B1 (en) * 1999-06-30 2002-03-26 Harris Corporation Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide
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US6235607B1 (en) * 1999-12-07 2001-05-22 Advanced Micro Devices, Inc. Method for establishing component isolation regions in SOI semiconductor device
US6476446B2 (en) 2000-01-03 2002-11-05 Advanced Micro Devices, Inc. Heat removal by removal of buried oxide in isolation areas
US6613643B1 (en) 2000-01-28 2003-09-02 Advanced Micro Devices, Inc. Structure, and a method of realizing, for efficient heat removal on SOI
US6767801B2 (en) 2000-03-10 2004-07-27 Nippon Steel Corporation Simox substrate and method for production thereof
US6486043B1 (en) 2000-08-31 2002-11-26 International Business Machines Corporation Method of forming dislocation filter in merged SOI and non-SOI chips
JP4501263B2 (ja) * 2000-09-20 2010-07-14 三菱マテリアル株式会社 Ｓｏｉ基板の製造方法
US6414355B1 (en) 2001-01-26 2002-07-02 Advanced Micro Devices, Inc. Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness
US6548369B1 (en) * 2001-03-20 2003-04-15 Advanced Micro Devices, Inc. Multi-thickness silicon films on a single semiconductor-on-insulator (SOI) chip using simox
JP2002289820A (ja) * 2001-03-28 2002-10-04 Nippon Steel Corp Ｓｉｍｏｘ基板の製造方法およびｓｉｍｏｘ基板
JP2002289552A (ja) 2001-03-28 2002-10-04 Nippon Steel Corp Ｓｉｍｏｘ基板の製造方法およびｓｉｍｏｘ基板
US6596570B2 (en) * 2001-06-06 2003-07-22 International Business Machines Corporation SOI device with reduced junction capacitance
US20030230778A1 (en) * 2002-01-30 2003-12-18 Sumitomo Mitsubishi Silicon Corporation SOI structure having a SiGe Layer interposed between the silicon and the insulator
US7535100B2 (en) * 2002-07-12 2009-05-19 The United States Of America As Represented By The Secretary Of The Navy Wafer bonding of thinned electronic materials and circuits to high performance substrates
TW577124B (en) * 2002-12-03 2004-02-21 Mosel Vitelic Inc Method for estimating the forming thickness of the oxide layer and determining whether the pipes occur leakages
US6770495B1 (en) * 2003-01-15 2004-08-03 Advanced Micro Devices, Inc. Method for revealing active regions in a SOI structure for DUT backside inspection
KR100947815B1 (ko) 2003-02-19 2010-03-15 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼
CN100472001C (zh) * 2003-02-25 2009-03-25 株式会社上睦可 硅晶片、soi衬底、硅单晶生长方法，硅晶片制造方法及soi衬底制造方法
US7112509B2 (en) * 2003-05-09 2006-09-26 Ibis Technology Corporation Method of producing a high resistivity SIMOX silicon substrate
AU2003297191A1 (en) * 2003-12-16 2005-07-14 International Business Machines Corporation Contoured insulator layer of silicon-on-onsulator wafers and process of manufacture
JP2005229062A (ja) * 2004-02-16 2005-08-25 Canon Inc Ｓｏｉ基板及びその製造方法
JP2006032785A (ja) * 2004-07-20 2006-02-02 Sumco Corp Ｓｏｉ基板の製造方法及びｓｏｉ基板
US7358586B2 (en) * 2004-09-28 2008-04-15 International Business Machines Corporation Silicon-on-insulator wafer having reentrant shape dielectric trenches
JP4609026B2 (ja) * 2004-10-06 2011-01-12 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP2006173568A (ja) 2004-12-14 2006-06-29 Korea Electronics Telecommun Ｓｏｉ基板の製造方法
US7211474B2 (en) * 2005-01-18 2007-05-01 International Business Machines Corporation SOI device with body contact self-aligned to gate
US7071047B1 (en) 2005-01-28 2006-07-04 International Business Machines Corporation Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions
US20060228492A1 (en) * 2005-04-07 2006-10-12 Sumco Corporation Method for manufacturing SIMOX wafer
JP4876442B2 (ja) 2005-06-13 2012-02-15 株式会社Ｓｕｍｃｏ Ｓｉｍｏｘウェーハの製造方法およびｓｉｍｏｘウェーハ
JP2007005563A (ja) 2005-06-23 2007-01-11 Sumco Corp Ｓｉｍｏｘウェーハの製造方法
KR100752182B1 (ko) * 2005-10-12 2007-08-24 동부일렉트로닉스 주식회사 씨모스 이미지 센서 및 그 제조방법
JP2007208023A (ja) 2006-02-02 2007-08-16 Sumco Corp Ｓｉｍｏｘウェーハの製造方法
JP2007227424A (ja) 2006-02-21 2007-09-06 Sumco Corp Ｓｉｍｏｘウェーハの製造方法
JP5157075B2 (ja) * 2006-03-27 2013-03-06 株式会社Ｓｕｍｃｏ Ｓｉｍｏｘウェーハの製造方法
JP5061489B2 (ja) 2006-04-05 2012-10-31 株式会社Ｓｕｍｃｏ Ｓｉｍｏｘウェーハの製造方法
JP2008244261A (ja) 2007-03-28 2008-10-09 Shin Etsu Handotai Co Ltd Ｓｏｉ基板の製造方法
US7955950B2 (en) * 2007-10-18 2011-06-07 International Business Machines Corporation Semiconductor-on-insulator substrate with a diffusion barrier
KR100937599B1 (ko) * 2007-12-17 2010-01-20 한국전자통신연구원 반도체 장치 및 그 형성 방법
FR2926925B1 (fr) * 2008-01-29 2010-06-25 Soitec Silicon On Insulator Procede de fabrication d'heterostructures
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
US7998815B2 (en) * 2008-08-15 2011-08-16 Qualcomm Incorporated Shallow trench isolation
KR100987794B1 (ko) 2008-12-22 2010-10-13 한국전자통신연구원 반도체 장치의 제조 방법
JP2009147383A (ja) * 2009-03-26 2009-07-02 Hitachi Kokusai Electric Inc 熱処理方法
JP5387451B2 (ja) * 2010-03-04 2014-01-15 信越半導体株式会社 Ｓｏｉウェーハの設計方法及び製造方法
JP2011176320A (ja) * 2011-03-07 2011-09-08 Hitachi Kokusai Electric Inc 基板処理装置
FR3034565B1 (fr) * 2015-03-30 2017-03-31 Soitec Silicon On Insulator Procede de fabrication d'une structure presentant une couche dielectrique enterree d'epaisseur uniforme
US9837334B2 (en) * 2015-03-30 2017-12-05 Globalfoundries Singapore Pte. Ltd. Programmable active cooling device
US11891821B2 (en) 2021-10-14 2024-02-06 John H. Kipp, Jr. Mini-concrete trowel attachment assembly

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FR2616590B1 (fr) * 1987-06-15 1990-03-02 Commissariat Energie Atomique Procede de fabrication d'une couche d'isolant enterree dans un substrat semi-conducteur par implantation ionique et structure semi-conductrice comportant cette couche
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Also Published As

Publication number Publication date
FI951340A (fi) 1995-09-24
FI951340A0 (fi) 1995-03-22
US5658809A (en) 1997-08-19
KR950027901A (ko) 1995-10-18
EP0675534A3 (de) 1996-11-13
EP0675534A2 (de) 1995-10-04
CZ281798B6 (cs) 1997-02-12
US5918136A (en) 1999-06-29
JPH07263538A (ja) 1995-10-13
EP0675534B1 (de) 2000-03-01
TW401609B (en) 2000-08-11
CZ72695A3 (en) 1995-11-15
DE69515189D1 (de) 2000-04-06
KR0145824B1 (ko) 1998-11-02
JP3036619B2 (ja) 2000-04-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SUMCO TECHXIV CORP., OMURA, NAGASAKI, JP

Owner name: NIPPON TELEGRAPH AND TELEPHONE CORP., TOKIO/TO, JP

Owner name: NTT ELECTRONICS CORP., TOKIO/TOKYO, JP