DE69430165D1 - Verriegelungsschaltungsgesteuerter Ausgangstreiber - Google Patents

Verriegelungsschaltungsgesteuerter Ausgangstreiber

Info

Publication number
DE69430165D1
DE69430165D1 DE69430165T DE69430165T DE69430165D1 DE 69430165 D1 DE69430165 D1 DE 69430165D1 DE 69430165 T DE69430165 T DE 69430165T DE 69430165 T DE69430165 T DE 69430165T DE 69430165 D1 DE69430165 D1 DE 69430165D1
Authority
DE
Germany
Prior art keywords
output driver
interlock circuit
circuit controlled
controlled output
interlock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69430165T
Other languages
English (en)
Other versions
DE69430165T2 (de
Inventor
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69430165D1 publication Critical patent/DE69430165D1/de
Application granted granted Critical
Publication of DE69430165T2 publication Critical patent/DE69430165T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69430165T 1993-09-30 1994-09-28 Verriegelungsschaltungsgesteuerter Ausgangstreiber Expired - Fee Related DE69430165T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/129,257 US5396108A (en) 1993-09-30 1993-09-30 Latch controlled output driver

Publications (2)

Publication Number Publication Date
DE69430165D1 true DE69430165D1 (de) 2002-04-25
DE69430165T2 DE69430165T2 (de) 2002-08-22

Family

ID=22439140

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69430165T Expired - Fee Related DE69430165T2 (de) 1993-09-30 1994-09-28 Verriegelungsschaltungsgesteuerter Ausgangstreiber

Country Status (4)

Country Link
US (1) US5396108A (de)
EP (1) EP0647028B1 (de)
JP (1) JP3526921B2 (de)
DE (1) DE69430165T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW294861B (de) * 1992-02-21 1997-01-01 Siemens Ag
JP3229164B2 (ja) * 1994-07-28 2001-11-12 インターナショナル・ビジネス・マシーンズ・コーポレーション ラッチ回路
US5845059A (en) * 1996-01-19 1998-12-01 Stmicroelectronics, Inc. Data-input device for generating test signals on bit and bit-complement lines
US5848018A (en) * 1996-01-19 1998-12-08 Stmicroelectronics, Inc. Memory-row selector having a test function
US5802004A (en) * 1996-01-19 1998-09-01 Sgs-Thomson Microelectronics, Inc. Clocked sense amplifier with wordline tracking
US5883838A (en) * 1996-01-19 1999-03-16 Stmicroelectronics, Inc. Device and method for driving a conductive path with a signal
JPH09282886A (ja) * 1996-01-19 1997-10-31 Sgs Thomson Microelectron Inc メモリセルへの書込の開始をトラッキングする回路及び方法
US5864696A (en) * 1996-01-19 1999-01-26 Stmicroelectronics, Inc. Circuit and method for setting the time duration of a write to a memory cell
US5691950A (en) * 1996-01-19 1997-11-25 Sgs-Thomson Microelectronics, Inc. Device and method for isolating bit lines from a data line
US5619466A (en) * 1996-01-19 1997-04-08 Sgs-Thomson Microelectronics, Inc. Low-power read circuit and method for controlling a sense amplifier
US5745432A (en) * 1996-01-19 1998-04-28 Sgs-Thomson Microelectronics, Inc. Write driver having a test function
JPH09231770A (ja) * 1996-01-19 1997-09-05 Sgs Thomson Microelectron Inc メモリセルへの書込を終了させる回路及び方法
US5777496A (en) * 1996-03-27 1998-07-07 Aeg Schneider Automation, Inc. Circuit for preventing more than one transistor from conducting
US5751178A (en) * 1996-12-05 1998-05-12 Motorola, Inc. Apparatus and method for shifting signal levels
US5864244A (en) * 1997-05-09 1999-01-26 Kaplinsky; Cecil H. Tristate buffer circuit with transparent latching capability
US5903180A (en) * 1997-07-24 1999-05-11 S3 Incorporated Voltage tolerant bus hold latch
JP4088466B2 (ja) * 2002-03-19 2008-05-21 三菱電機株式会社 パワーデバイスの駆動回路
US6995598B2 (en) * 2003-02-13 2006-02-07 Texas Instruments Incorporated Level shifter circuit including a set/reset circuit
US6828838B1 (en) * 2003-05-30 2004-12-07 Intel Corporation Vectored flip-flops and latches with embedded output-merge logic and shared clock drivers
JP4014048B2 (ja) * 2004-06-02 2007-11-28 ローム株式会社 コイル負荷駆動出力回路
US8030960B2 (en) * 2008-12-29 2011-10-04 Oracle America, Inc. Converting dynamic repeaters to conventional repeaters
US8063673B2 (en) * 2008-12-29 2011-11-22 Oracle America, Inc. Transit state element
US9647456B2 (en) * 2014-03-13 2017-05-09 Nxp B.V. Power management circuit and a method for operating a power management circuit
US9570158B1 (en) * 2016-05-04 2017-02-14 Qualcomm Incorporated Output latch for accelerated memory access

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6335009A (ja) * 1986-07-30 1988-02-15 Toshiba Corp 半導体回路
JPH073945B2 (ja) * 1988-06-27 1995-01-18 日本電気株式会社 Ｃｍｏｓ出力回路
JPH02226589A (ja) * 1989-02-27 1990-09-10 Nec Corp 半導体記憶装置
JPH02243015A (ja) * 1989-03-15 1990-09-27 Nec Corp 制御回路
US5001369A (en) * 1990-07-02 1991-03-19 Micron Technology, Inc. Low noise output buffer circuit

Also Published As

Publication number Publication date
US5396108A (en) 1995-03-07
EP0647028A3 (de) 1996-01-24
JP3526921B2 (ja) 2004-05-17
EP0647028A2 (de) 1995-04-05
JPH07170159A (ja) 1995-07-04
DE69430165T2 (de) 2002-08-22
EP0647028B1 (de) 2002-03-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee