DE69329788T2 - Direktzugriffspeicherentwurf - Google Patents
DirektzugriffspeicherentwurfInfo
- Publication number
- DE69329788T2 DE69329788T2 DE69329788T DE69329788T DE69329788T2 DE 69329788 T2 DE69329788 T2 DE 69329788T2 DE 69329788 T DE69329788 T DE 69329788T DE 69329788 T DE69329788 T DE 69329788T DE 69329788 T2 DE69329788 T2 DE 69329788T2
- Authority
- DE
- Germany
- Prior art keywords
- random access
- access memory
- memory design
- design
- random
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US96061692A | 1992-10-14 | 1992-10-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69329788D1 DE69329788D1 (de) | 2001-02-01 |
DE69329788T2 true DE69329788T2 (de) | 2001-08-02 |
Family
ID=25503399
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69329788T Expired - Fee Related DE69329788T2 (de) | 1992-10-14 | 1993-07-30 | Direktzugriffspeicherentwurf |
Country Status (5)
Country | Link |
---|---|
US (1) | US5570319A (de) |
EP (1) | EP0593152B1 (de) |
JP (1) | JP3575490B2 (de) |
KR (1) | KR100346356B1 (de) |
DE (1) | DE69329788T2 (de) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0669620B1 (de) * | 1994-02-25 | 2001-10-24 | Kabushiki Kaisha Toshiba | Multiplexer |
US5537346A (en) * | 1994-05-20 | 1996-07-16 | Samsung Electronics Co., Ltd. | Semiconductor memory device obtaining high bandwidth and signal line layout method thereof |
US5701269A (en) * | 1994-11-28 | 1997-12-23 | Fujitsu Limited | Semiconductor memory with hierarchical bit lines |
WO1996031882A1 (en) * | 1995-04-05 | 1996-10-10 | Micron Technology, Inc. | Memory circuit with hierarchical bit line structure |
US5600602A (en) * | 1995-04-05 | 1997-02-04 | Micron Technology, Inc. | Hierarchical memory array structure having electrically isolated bit lines for temporary data storage |
US5734620A (en) * | 1995-04-05 | 1998-03-31 | Micron Technology, Inc. | Hierarchical memory array structure with redundant components having electrically isolated bit lines |
EP0741387B1 (de) * | 1995-05-05 | 2000-01-12 | STMicroelectronics S.r.l. | Nichtflüchtige Speicheranordnung mit Sektoren, deren Grösse und Anzahl bestimmbar sind |
EP0741415A1 (de) * | 1995-05-05 | 1996-11-06 | STMicroelectronics S.r.l. | Flash-EEPROM-Speicher mit kontaktlosen Speicherzellen |
JPH09161476A (ja) * | 1995-10-04 | 1997-06-20 | Toshiba Corp | 半導体メモリ及びそのテスト回路、並びにデ−タ転送システム |
US5802004A (en) * | 1996-01-19 | 1998-09-01 | Sgs-Thomson Microelectronics, Inc. | Clocked sense amplifier with wordline tracking |
TW318933B (en) * | 1996-03-08 | 1997-11-01 | Hitachi Ltd | Semiconductor IC device having a memory and a logic circuit implemented with a single chip |
JP3579205B2 (ja) * | 1996-08-06 | 2004-10-20 | 株式会社ルネサステクノロジ | 半導体記憶装置、半導体装置、データ処理装置及びコンピュータシステム |
EP0834881A1 (de) * | 1996-10-01 | 1998-04-08 | STMicroelectronics S.r.l. | Mehrfachblock-Speicher |
US5991217A (en) * | 1996-12-26 | 1999-11-23 | Micro Magic, Inc. | Fast SRAM design using embedded sense amps |
JP3248468B2 (ja) * | 1997-10-30 | 2002-01-21 | 日本電気株式会社 | 半導体記憶装置 |
US6351427B1 (en) * | 1997-12-10 | 2002-02-26 | Texas Instruments Incorporated | Stored write scheme for high speed/wide bandwidth memory devices |
US6058065A (en) * | 1998-05-21 | 2000-05-02 | International Business Machines Corporation | Memory in a data processing system having improved performance and method therefor |
US5963486A (en) * | 1998-06-19 | 1999-10-05 | International Business Machines Corporation | Bit switch circuit and bit line selection method |
US6031784A (en) * | 1998-09-04 | 2000-02-29 | G-Link Technology | Hierarchical decoding of a memory device |
US6014338A (en) * | 1998-12-23 | 2000-01-11 | Sun Microsystems, Inc. | Single ended read scheme with global bitline of multi-port register file |
US6865099B2 (en) * | 1999-01-14 | 2005-03-08 | Silicon Storage Technology, Inc. | Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory |
US6282145B1 (en) * | 1999-01-14 | 2001-08-28 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US6178134B1 (en) * | 1999-09-21 | 2001-01-23 | Lucent Technologies, Inc. | Static random access memory with global bit-lines |
US6249470B1 (en) | 1999-12-03 | 2001-06-19 | International Business Machines Corporation | Bi-directional differential low power sense amp and memory system |
US6226216B1 (en) * | 2000-01-21 | 2001-05-01 | Intel Corporation | Sectional column activated memory |
JP3860403B2 (ja) * | 2000-09-25 | 2006-12-20 | 株式会社東芝 | 半導体メモリ装置 |
US6714467B2 (en) * | 2002-03-19 | 2004-03-30 | Broadcom Corporation | Block redundancy implementation in heirarchical RAM's |
US6646954B2 (en) * | 2001-02-02 | 2003-11-11 | Broadcom Corporation | Synchronous controlled, self-timed local SRAM block |
US6876567B2 (en) * | 2001-12-21 | 2005-04-05 | Intel Corporation | Ferroelectric memory device and method of reading a ferroelectric memory |
US8233322B2 (en) * | 2003-10-10 | 2012-07-31 | Micron Technology, Inc. | Multi-partition memory with separated read and algorithm datalines |
FR2881564B1 (fr) | 2005-02-02 | 2007-06-01 | St Microelectronics Sa | Circuit integre de memoire, en particulier de memoire sram et procede de fabrication correspondant |
US7085173B1 (en) * | 2005-02-09 | 2006-08-01 | International Business Machines Corporation | Write driver circuit for memory array |
US7310257B2 (en) * | 2005-11-10 | 2007-12-18 | Micron Technology, Inc. | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells |
US7376027B1 (en) * | 2006-11-07 | 2008-05-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | DRAM concurrent writing and sensing scheme |
US7643367B2 (en) * | 2007-08-15 | 2010-01-05 | Oki Semiconductor Co., Ltd. | Semiconductor memory device |
US7848131B2 (en) * | 2008-10-19 | 2010-12-07 | Juhan Kim | High speed ferroelectric random access memory |
US20150138863A1 (en) * | 2013-11-15 | 2015-05-21 | Lsi Corporation | Interleaved write assist for hierarchical bitline sram architectures |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5132930A (en) * | 1986-07-31 | 1992-07-21 | Mitsubishi Denki Kabushiki Kaisha | CMOS dynamic memory device having multiple flip-flop circuits selectively coupled to form sense amplifiers specific to neighboring data bit lines |
EP0258715B1 (de) * | 1986-08-15 | 1994-06-08 | Nec Corporation | Statischer Direktzugriffspeicher einer Bi-CMOS-Konstruktion |
JPH01267891A (ja) * | 1988-04-18 | 1989-10-25 | Seiko Epson Corp | 半導体記憶装置 |
DE59010018D1 (de) * | 1989-04-21 | 1996-02-15 | Siemens Ag | Statischer Speicher |
JP2626160B2 (ja) * | 1990-04-27 | 1997-07-02 | 日本電気株式会社 | 半導体メモリ |
JP2744144B2 (ja) * | 1991-03-14 | 1998-04-28 | 株式会社東芝 | 半導体記憶装置 |
-
1993
- 1993-07-30 DE DE69329788T patent/DE69329788T2/de not_active Expired - Fee Related
- 1993-07-30 EP EP93306032A patent/EP0593152B1/de not_active Expired - Lifetime
- 1993-09-28 JP JP26303793A patent/JP3575490B2/ja not_active Expired - Fee Related
- 1993-10-04 KR KR1019930020425A patent/KR100346356B1/ko not_active IP Right Cessation
-
1995
- 1995-08-31 US US08/522,061 patent/US5570319A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0593152B1 (de) | 2000-12-27 |
DE69329788D1 (de) | 2001-02-01 |
KR940010353A (ko) | 1994-05-26 |
KR100346356B1 (ko) | 2002-11-18 |
JP3575490B2 (ja) | 2004-10-13 |
JPH06209083A (ja) | 1994-07-26 |
EP0593152A3 (en) | 1995-10-04 |
EP0593152A2 (de) | 1994-04-20 |
US5570319A (en) | 1996-10-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |