DE69329761T2 - Differenzflaggeschaltung mit verschobenem Zähler - Google Patents

Differenzflaggeschaltung mit verschobenem Zähler

Info

Publication number
DE69329761T2
DE69329761T2 DE69329761T DE69329761T DE69329761T2 DE 69329761 T2 DE69329761 T2 DE 69329761T2 DE 69329761 T DE69329761 T DE 69329761T DE 69329761 T DE69329761 T DE 69329761T DE 69329761 T2 DE69329761 T2 DE 69329761T2
Authority
DE
Germany
Prior art keywords
flag circuit
shifted counter
differential flag
differential
shifted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69329761T
Other languages
English (en)
Other versions
DE69329761D1 (de
Inventor
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69329761D1 publication Critical patent/DE69329761D1/de
Application granted granted Critical
Publication of DE69329761T2 publication Critical patent/DE69329761T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
DE69329761T 1992-06-22 1993-06-10 Differenzflaggeschaltung mit verschobenem Zähler Expired - Fee Related DE69329761T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/901,667 US5355113A (en) 1992-06-22 1992-06-22 Serialized difference flag circuit

Publications (2)

Publication Number Publication Date
DE69329761D1 DE69329761D1 (de) 2001-01-25
DE69329761T2 true DE69329761T2 (de) 2001-05-10

Family

ID=25414612

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69329761T Expired - Fee Related DE69329761T2 (de) 1992-06-22 1993-06-10 Differenzflaggeschaltung mit verschobenem Zähler

Country Status (4)

Country Link
US (1) US5355113A (de)
EP (1) EP0579375B1 (de)
JP (1) JPH0675745A (de)
DE (1) DE69329761T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5852748A (en) * 1995-12-29 1998-12-22 Cypress Semiconductor Corp. Programmable read-write word line equality signal generation for FIFOs
US5900013A (en) * 1996-07-26 1999-05-04 Advanced Micro Devices, Inc. Dual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entries
US5960468A (en) * 1997-04-30 1999-09-28 Sony Corporation Asynchronous memory interface for a video processor with a 2N sized buffer and N+1 bit wide gray coded counters
US6041418A (en) * 1998-08-07 2000-03-21 Lucent Technologies, Inc. Race free and technology independent flag generating circuitry associated with two asynchronous clocks
US6732223B1 (en) 2000-04-03 2004-05-04 Micron Technology, Inc. Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system
US6480912B1 (en) 2000-07-21 2002-11-12 Stmicroelectronics, Inc. Method and apparatus for determining the number of empty memory locations in a FIFO memory device
US7116599B1 (en) * 2001-09-20 2006-10-03 Cypress Semiconductor Corp. High speed FIFO synchronous programmable full and empty flag generation
US7149938B1 (en) * 2001-12-07 2006-12-12 Applied Micro Circuits Corporation Non-causal channel equalization
US8161366B2 (en) * 2007-12-03 2012-04-17 International Business Machines Corporation Finite state machine error recovery

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3196283A (en) * 1960-05-26 1965-07-20 Cutler Hammer Inc Pulse amplitude comparator
US3278761A (en) * 1964-07-17 1966-10-11 Rca Corp Differential amplifier having a high output impedance for differential input signals and a low output impedance for common mode signals
US5027330A (en) * 1988-12-30 1991-06-25 At&T Bell Laboratories FIFO memory arrangement including a memory location fill indication
US4935719A (en) * 1989-03-31 1990-06-19 Sgs-Thomson Microelectronics, Inc. Comparator circuitry
US4969164A (en) * 1989-04-27 1990-11-06 Advanced Micro Devices, Inc. Programmable threshold detection logic for a digital storage buffer
US5084841A (en) * 1989-08-14 1992-01-28 Texas Instruments Incorporated Programmable status flag generator FIFO using gray code
US5357236A (en) * 1992-05-29 1994-10-18 Sgs-Thomson Microelectronics, Inc. Parallelized difference flag logic

Also Published As

Publication number Publication date
DE69329761D1 (de) 2001-01-25
EP0579375A3 (de) 1994-01-26
JPH0675745A (ja) 1994-03-18
EP0579375B1 (de) 2000-12-20
US5355113A (en) 1994-10-11
EP0579375A2 (de) 1994-01-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee