DE69317507D1 - Fehlertolerantes Rechnersystem mit einem in jedem Prozessormodul vorgesehenen Fehlerdetektor - Google Patents

Fehlertolerantes Rechnersystem mit einem in jedem Prozessormodul vorgesehenen Fehlerdetektor

Info

Publication number
DE69317507D1
DE69317507D1 DE69317507T DE69317507T DE69317507D1 DE 69317507 D1 DE69317507 D1 DE 69317507D1 DE 69317507 T DE69317507 T DE 69317507T DE 69317507 T DE69317507 T DE 69317507T DE 69317507 D1 DE69317507 D1 DE 69317507D1
Authority
DE
Germany
Prior art keywords
fault
module
modules
output signal
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69317507T
Other languages
English (en)
Other versions
DE69317507T2 (de
Inventor
Hiroaki Miyoshi
Yasuhiko Mizushima
Makoto Ohtsuka
Hiroki Hihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Space Technologies Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69317507D1 publication Critical patent/DE69317507D1/de
Publication of DE69317507T2 publication Critical patent/DE69317507T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1654Error detection by comparing the output of redundant processing systems where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1641Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/18Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/181Eliminating the failing redundant component
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/18Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/18Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
DE69317507T 1992-11-06 1993-11-05 Fehlertolerantes Rechnersystem mit einem in jedem Prozessormodul vorgesehenen Fehlerdetektor Expired - Lifetime DE69317507T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4296942A JPH0760395B2 (ja) 1992-11-06 1992-11-06 フォールトトレラントコンピュータシステム

Publications (2)

Publication Number Publication Date
DE69317507D1 true DE69317507D1 (de) 1998-04-23
DE69317507T2 DE69317507T2 (de) 1998-07-09

Family

ID=17840180

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69317507T Expired - Lifetime DE69317507T2 (de) 1992-11-06 1993-11-05 Fehlertolerantes Rechnersystem mit einem in jedem Prozessormodul vorgesehenen Fehlerdetektor

Country Status (4)

Country Link
US (1) US5485604A (de)
EP (1) EP0596516B1 (de)
JP (1) JPH0760395B2 (de)
DE (1) DE69317507T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864654A (en) * 1995-03-31 1999-01-26 Nec Electronics, Inc. Systems and methods for fault tolerant information processing
JP2738338B2 (ja) * 1995-04-24 1998-04-08 日本電気株式会社 フォールトトレラントシステム
US5887146A (en) * 1995-08-14 1999-03-23 Data General Corporation Symmetric multiprocessing computer with non-uniform memory access architecture
JPH11143729A (ja) 1997-11-07 1999-05-28 Nec Corp フォールトトレラントコンピュータ
JPH11203157A (ja) * 1998-01-13 1999-07-30 Fujitsu Ltd 冗長装置
JP3794151B2 (ja) * 1998-02-16 2006-07-05 株式会社日立製作所 クロスバースイッチを有する情報処理装置およびクロスバースイッチ制御方法
US7257734B2 (en) * 2003-07-17 2007-08-14 International Business Machines Corporation Method and apparatus for managing processors in a multi-processor data processing system
JP4318211B2 (ja) * 2004-03-08 2009-08-19 富士通株式会社 高信頼システム、冗長構成制御方法及びプログラム
US8137382B2 (en) * 2004-11-05 2012-03-20 Biomet Sports Medicine, Llc Method and apparatus for coupling anatomical features
JP4795025B2 (ja) * 2006-01-13 2011-10-19 キヤノン株式会社 ダイナミックリコンフィギャラブルデバイス、制御方法、及びプログラム
JP2007251495A (ja) * 2006-03-15 2007-09-27 Fujitsu Ltd 電子機器
JP2007293701A (ja) * 2006-04-26 2007-11-08 Canon Inc 動的再構成可能デバイスの制御装置及び方法
US7478299B2 (en) * 2006-08-14 2009-01-13 International Business Machines Corporation Processor fault isolation
JP4491479B2 (ja) * 2007-09-27 2010-06-30 株式会社日立製作所 分散制御システム
JP5272442B2 (ja) 2008-02-20 2013-08-28 日本電気株式会社 ブレードサーバ、及びスイッチブレード
JP2010071538A (ja) * 2008-09-18 2010-04-02 Hitachi Kokusai Electric Inc 射撃訓練システム
CN101706767B (zh) * 2009-08-13 2012-08-08 北京大学深圳研究生院 一种阵列处理器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1253309A (en) * 1969-11-21 1971-11-10 Marconi Co Ltd Improvements in or relating to data processing arrangements
DE2202231A1 (de) * 1972-01-18 1973-07-26 Siemens Ag Verarbeitungssystem mit verdreifachten systemeinheiten
DE2303828A1 (de) * 1973-01-26 1974-08-01 Standard Elektrik Lorenz Ag Steuerverfahren mit drei parallel betriebenen rechnern
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
DE2939487A1 (de) * 1979-09-28 1981-04-16 Siemens AG, 1000 Berlin und 8000 München Rechnerarchitektur auf der basis einer multi-mikrocomputerstruktur als fehlertolerantes system
DE3108871A1 (de) * 1981-03-09 1982-09-16 Siemens AG, 1000 Berlin und 8000 München Einrichtung zur funktionspruefung eines mehrrechnersystems
DE3275595D1 (en) * 1981-10-01 1987-04-09 Stratus Computer Inc Digital data processor with fault-tolerant bus protocol
JPS61283954A (ja) * 1985-06-10 1986-12-13 Nippon Telegr & Teleph Corp <Ntt> 並列計算機の故障検出方法
ATE110477T1 (de) * 1990-08-14 1994-09-15 Siemens Ag Mehrrechnersystem hoher sicherheit mit drei rechnern.

Also Published As

Publication number Publication date
JPH0760395B2 (ja) 1995-06-28
EP0596516A2 (de) 1994-05-11
DE69317507T2 (de) 1998-07-09
EP0596516A3 (en) 1994-09-14
US5485604A (en) 1996-01-16
EP0596516B1 (de) 1998-03-18
JPH06149605A (ja) 1994-05-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC TOSHIBA SPACE SYSTEMS, LTD., YOKOHAMA, KANAGAW