DE69132247T2 - Phasenverriegelte Schleifenanordnung - Google Patents

Phasenverriegelte Schleifenanordnung

Info

Publication number
DE69132247T2
DE69132247T2 DE69132247T DE69132247T DE69132247T2 DE 69132247 T2 DE69132247 T2 DE 69132247T2 DE 69132247 T DE69132247 T DE 69132247T DE 69132247 T DE69132247 T DE 69132247T DE 69132247 T2 DE69132247 T2 DE 69132247T2
Authority
DE
Germany
Prior art keywords
locked loop
phase locked
loop arrangement
dual
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132247T
Other languages
English (en)
Other versions
DE69132247D1 (de
Inventor
David Lawrence Archer
Timothy Charles Rayner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA filed Critical Alcatel SA
Publication of DE69132247D1 publication Critical patent/DE69132247D1/de
Application granted granted Critical
Publication of DE69132247T2 publication Critical patent/DE69132247T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
  • Materials For Medical Uses (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Dc Digital Transmission (AREA)
DE69132247T 1990-03-14 1991-01-22 Phasenverriegelte Schleifenanordnung Expired - Fee Related DE69132247T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AUPJ910490 1990-03-14

Publications (2)

Publication Number Publication Date
DE69132247D1 DE69132247D1 (de) 2000-07-13
DE69132247T2 true DE69132247T2 (de) 2000-12-21

Family

ID=3774550

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132247T Expired - Fee Related DE69132247T2 (de) 1990-03-14 1991-01-22 Phasenverriegelte Schleifenanordnung

Country Status (7)

Country Link
US (1) US5255293A (de)
EP (1) EP0450269B1 (de)
JP (1) JPH0738545A (de)
AT (1) ATE193791T1 (de)
CA (1) CA2038102C (de)
DE (1) DE69132247T2 (de)
ES (1) ES2146576T3 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI90709C (fi) * 1992-02-14 1994-03-10 Nokia Telecommunications Oy Järjestely osoitinvärinän vaimentamiseksi desynkronisaattorissa
US5691976A (en) * 1992-04-02 1997-11-25 Applied Digital Access Performance monitoring and test system for a telephone network
FI90486C (fi) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Menetelmä ja laite synkronisessa digitaalisessa tietoliikennejärjestelmässä suoritettavan elastisen puskuroinnin toteuttamiseksi
GB9323187D0 (en) * 1993-11-10 1994-01-05 Northern Telecom Ltd Pointer justification even leak control
IT1265424B1 (it) * 1993-12-22 1996-11-22 Alcatel Italia Metodo e disposizione ciruitale di realizzazione della funzione di hpa negli apparati sdh
GB9405748D0 (en) * 1994-03-23 1994-05-11 Plessey Telecomm Complementary justification algorithm
US5883900A (en) * 1994-03-23 1999-03-16 Gpt Limited Telecommunications transmission
US5757872A (en) * 1994-11-30 1998-05-26 Lucent Technologies Inc. Clock recovery circuit
DE4442506A1 (de) * 1994-11-30 1996-06-05 Sel Alcatel Ag Synchronisierungsüberachung in einem Netzwerk
US6202108B1 (en) * 1997-03-13 2001-03-13 Bull S.A. Process and system for initializing a serial link between two integrated circuits comprising a parallel-serial port using two clocks with different frequencies
DE69735527D1 (de) 1997-05-02 2006-05-11 Lsi Logic Corp Digitales Verfahren zur adaptiven Taktrückgewinnung
US6370158B1 (en) 1997-11-14 2002-04-09 Wireless Facilities, Inc. Wireless T/E Transceiver frame signaling subcontroller
DE19943779A1 (de) 1999-09-13 2001-03-22 Siemens Ag Anordnung zum Synchronisieren von über ein Kommunikationsnetz gekoppelten Kommunikationssystemkomponenten
US6463111B1 (en) * 2001-05-25 2002-10-08 Transwitch Corporaton Method and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS-STM payload
DE10136662A1 (de) * 2001-07-27 2003-02-13 Siemens Ag Verfahren und Anordnung zur Anpassung der Taktraten digitaler Signale
US6910145B2 (en) * 2001-12-13 2005-06-21 Emc Corporation Data transmission across asynchronous clock domains
US7123675B2 (en) * 2002-09-25 2006-10-17 Lucent Technologies Inc. Clock, data and time recovery using bit-resolved timing registers
US8094562B1 (en) * 2004-06-24 2012-01-10 Cypress Semiconductor Corporation Transmission of a continuous datastream through a re-clocked frame-based transport network
US20070220184A1 (en) * 2006-03-17 2007-09-20 International Business Machines Corporation Latency-locked loop (LLL) circuit, buffer including the circuit, and method of adjusting a data rate
US7984209B1 (en) * 2006-12-12 2011-07-19 Altera Corporation Data interface methods and circuitry with reduced latency

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE414104B (sv) * 1978-10-13 1980-07-07 Ellemtel Utvecklings Ab Digital faslast slinga
US4347620A (en) * 1980-09-16 1982-08-31 Northern Telecom Limited Method of and apparatus for regenerating a signal frequency in a digital signal transmission system
DE3309270A1 (de) * 1983-03-15 1984-09-20 Siemens AG, 1000 Berlin und 8000 München Synchronisation nachziehbarer taktoszillatoren bei der uebertragung digitaler signale
US4876700A (en) * 1986-04-16 1989-10-24 E. F. Johnson Company Data demodulator
US4791652A (en) * 1987-06-04 1988-12-13 Northern Telecom Limited Synchronization of asynchronous data signals
US4882754A (en) * 1987-08-25 1989-11-21 Digideck, Inc. Data compression system and method with buffer control

Also Published As

Publication number Publication date
US5255293A (en) 1993-10-19
ATE193791T1 (de) 2000-06-15
JPH0738545A (ja) 1995-02-07
DE69132247D1 (de) 2000-07-13
CA2038102A1 (en) 1991-09-15
EP0450269B1 (de) 2000-06-07
ES2146576T3 (es) 2000-08-16
CA2038102C (en) 1996-04-16
EP0450269A3 (de) 1994-03-30
EP0450269A2 (de) 1991-10-09

Similar Documents

Publication Publication Date Title
DE69132247T2 (de) Phasenverriegelte Schleifenanordnung
EP0491054B1 (de) Anordnung zum extrahieren von asynchronen signalen
EP0244122A3 (en) Clock recovery digital phase-locked loop
EP0286329A3 (de) Synchronisator und Signaldetektor mit Phasenregelschleife
AU4444196A (en) Incremental desynchronizer
SE9503702L (sv) Fastlåst loop
FI923166A (fi) Sdh dataoeverfoeringssystem
DE69219928D1 (de) Übertragung von Multiplexdaten in einem Ring
CA2055823A1 (en) Clock information transmitting device and clock information receiving device
ATE14058T1 (de) Digitales nachrichtenuebertragungssystem.
EP0742653A3 (de) PDH/SDH-Signalprozessor mit Taktgenerator mit zwei Betriebsarten
GB2296397A (en) Digital phase locked loop
GB2279522A (en) Pointer jitter suppression in a desynchronizer
EP0374537A3 (de) Demultiplexer mit Schaltung zur Verringerung des Wartezeitjitters
EP0492549A3 (en) Method for the reduction of phase noise introduced by the sdh network (synchronous digital hierarchy network) by pointer justification and integrated circuits for the implementation of the method
CA2063930A1 (en) Synchronous digital signal to asynchronous digital signal desynchronizer
JPS5742288A (en) Rotating information recording medium reproduction device
GB1527732A (en) Digital phase locked loop
JPS5564637A (en) Pcm recording and reproducing device
DE59307881D1 (de) Anordnung zur Erzeugung eines Taktsignals mit bitgenauen Lücken
Cataltepe et al. Proposed Values for Remaining" TBD" s in the Draft ANSI Standard, T1. 105.09
JPS5550775A (en) Phase alignment system
DE59204465D1 (de) Phasenregelkreis.
JPS63209241A (ja) 時分割方向制御伝送におけるクロツク抽出方式
TW267277B (en) Digital phase-locked loop

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ALCATEL LUCENT, PARIS, FR

8339 Ceased/non-payment of the annual fee