DE69131458D1 - Hardware-Anordnung zur Addition und Subtraktion von Gleitkommazahlen - Google Patents

Hardware-Anordnung zur Addition und Subtraktion von Gleitkommazahlen

Info

Publication number
DE69131458D1
DE69131458D1 DE69131458T DE69131458T DE69131458D1 DE 69131458 D1 DE69131458 D1 DE 69131458D1 DE 69131458 T DE69131458 T DE 69131458T DE 69131458 T DE69131458 T DE 69131458T DE 69131458 D1 DE69131458 D1 DE 69131458D1
Authority
DE
Germany
Prior art keywords
floating point
point numbers
hardware arrangement
subtracting floating
subtracting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131458T
Other languages
English (en)
Other versions
DE69131458T2 (de
Inventor
Takashi Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69131458D1 publication Critical patent/DE69131458D1/de
Publication of DE69131458T2 publication Critical patent/DE69131458T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE69131458T 1990-10-31 1991-10-31 Hardware-Anordnung zur Addition und Subtraktion von Gleitkommazahlen Expired - Fee Related DE69131458T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2296067A JP2508912B2 (ja) 1990-10-31 1990-10-31 浮動小数点加算装置

Publications (2)

Publication Number Publication Date
DE69131458D1 true DE69131458D1 (de) 1999-08-26
DE69131458T2 DE69131458T2 (de) 2000-03-23

Family

ID=17828682

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131458T Expired - Fee Related DE69131458T2 (de) 1990-10-31 1991-10-31 Hardware-Anordnung zur Addition und Subtraktion von Gleitkommazahlen

Country Status (4)

Country Link
US (1) US5197023A (de)
EP (1) EP0483864B1 (de)
JP (1) JP2508912B2 (de)
DE (1) DE69131458T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0551531A1 (de) * 1991-12-20 1993-07-21 International Business Machines Corporation Gerät zur Ausführung von Addierungs-/Substrahierungsoperationen auf IEEE-Standard-Gleitkommazahlen
US5408426A (en) * 1992-03-17 1995-04-18 Hitachi, Ltd. Arithmetic unit capable of performing concurrent operations for high speed operation
US5373461A (en) * 1993-01-04 1994-12-13 Motorola, Inc. Data processor a method and apparatus for performing postnormalization in a floating-point execution unit
US5339266A (en) * 1993-11-29 1994-08-16 Motorola, Inc. Parallel method and apparatus for detecting and completing floating point operations involving special operands
US5430668A (en) * 1994-03-07 1995-07-04 Nec Corporation Floating point multiplier capable of easily performing a failure detection test
US5757682A (en) * 1995-03-31 1998-05-26 International Business Machines Corporation Parallel calculation of exponent and sticky bit during normalization
US5764556A (en) * 1995-07-18 1998-06-09 Advanced Micro Devices, Inc. Method and apparatus for performing floating point addition
KR970016936A (ko) * 1995-09-06 1997-04-28 엘리 와이스 최상위 디지트를 결정하는 장치 및 방법
US5798967A (en) * 1997-02-22 1998-08-25 Programmable Microelectronics Corporation Sensing scheme for non-volatile memories
US6094668A (en) * 1997-10-23 2000-07-25 Advanced Micro Devices, Inc. Floating point arithmetic unit including an efficient close data path
US6088715A (en) * 1997-10-23 2000-07-11 Advanced Micro Devices, Inc. Close path selection unit for performing effective subtraction within a floating point arithmetic unit
US6085212A (en) * 1997-10-23 2000-07-04 Advanced Micro Devices, Inc. Efficient method for performing close path subtraction in a floating point arithmetic unit
US6301594B1 (en) * 1999-03-11 2001-10-09 Sun Microsystems, Inc. Method and apparatus for high-speed exponent adjustment and exception generation for normalization of floating-point numbers
KR100331846B1 (ko) * 1999-04-02 2002-04-09 박종섭 실수 연산기
US20030055859A1 (en) * 2001-05-04 2003-03-20 Southern Methodist University Fast IEEE floating-point adder
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US20020184566A1 (en) * 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US20030028696A1 (en) * 2001-06-01 2003-02-06 Michael Catherwood Low overhead interrupt
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6952711B2 (en) * 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6975679B2 (en) * 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US6976158B2 (en) * 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US20030005269A1 (en) * 2001-06-01 2003-01-02 Conner Joshua M. Multi-precision barrel shifting
US20030005268A1 (en) * 2001-06-01 2003-01-02 Catherwood Michael I. Find first bit value instruction
US6937084B2 (en) * 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US20030023836A1 (en) * 2001-06-01 2003-01-30 Michael Catherwood Shadow register array control instructions
US7020788B2 (en) * 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US6934728B2 (en) * 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6985986B2 (en) * 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US7467178B2 (en) * 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
US8543632B2 (en) * 2003-06-11 2013-09-24 Stmicroelectronics, Inc. Method and system for computing alignment sticky bit in floating-point operations
US7720898B2 (en) * 2003-06-11 2010-05-18 Stmicroelectronics, Inc. Apparatus and method for adjusting exponents of floating point numbers
US7395306B1 (en) * 2003-09-03 2008-07-01 Advanced Micro Devices, Inc. Fast add rotate add operation
US7730117B2 (en) * 2005-02-09 2010-06-01 International Business Machines Corporation System and method for a floating point unit with feedback prior to normalization and rounding
JP4232838B2 (ja) * 2007-03-29 2009-03-04 日本電気株式会社 再構成可能なｓｉｍｄ型プロセッサ
US10346130B2 (en) * 2017-05-12 2019-07-09 Arm Limited Handling floating point operations

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608933A (ja) * 1983-06-28 1985-01-17 Nec Corp 演算処理装置
US4849923A (en) * 1986-06-27 1989-07-18 Digital Equipment Corporation Apparatus and method for execution of floating point operations
JPH0664529B2 (ja) * 1987-03-13 1994-08-22 日本電信電話株式会社 丸め加算器
JPH01302425A (ja) * 1988-05-31 1989-12-06 Toshiba Corp 浮動小数点加減算回路
US4994996A (en) * 1989-02-03 1991-02-19 Digital Equipment Corporation Pipelined floating point adder for digital computer
US5027308A (en) * 1989-02-14 1991-06-25 Intel Corporation Circuit for adding/subtracting two floating point operands
US4999803A (en) * 1989-06-29 1991-03-12 Digital Equipment Corporation Floating point arithmetic system and method
US5128889A (en) * 1990-02-22 1992-07-07 Matsushita Electric Industrial Co., Ltd. Floating-point arithmetic apparatus with compensation for mantissa truncation

Also Published As

Publication number Publication date
DE69131458T2 (de) 2000-03-23
EP0483864B1 (de) 1999-07-21
JP2508912B2 (ja) 1996-06-19
EP0483864A2 (de) 1992-05-06
US5197023A (en) 1993-03-23
EP0483864A3 (en) 1993-03-24
JPH04167125A (ja) 1992-06-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee