DE69128319D1 - Arbeitsplatz mit Stossbetriebdatenübertragung - Google Patents

Arbeitsplatz mit Stossbetriebdatenübertragung

Info

Publication number
DE69128319D1
DE69128319D1 DE69128319T DE69128319T DE69128319D1 DE 69128319 D1 DE69128319 D1 DE 69128319D1 DE 69128319 T DE69128319 T DE 69128319T DE 69128319 T DE69128319 T DE 69128319T DE 69128319 D1 DE69128319 D1 DE 69128319D1
Authority
DE
Germany
Prior art keywords
workplace
data transmission
operation data
burst operation
burst
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128319T
Other languages
English (en)
Other versions
DE69128319T2 (de
Inventor
Anton Goeppel
Edward C King
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc filed Critical NCR International Inc
Publication of DE69128319D1 publication Critical patent/DE69128319D1/de
Application granted granted Critical
Publication of DE69128319T2 publication Critical patent/DE69128319T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
DE69128319T 1990-08-31 1991-08-30 Arbeitsplatz mit Stossbetriebdatenübertragung Expired - Fee Related DE69128319T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB909019023A GB9019023D0 (en) 1990-08-31 1990-08-31 Work station having multiplexing and burst mode capabilities

Publications (2)

Publication Number Publication Date
DE69128319D1 true DE69128319D1 (de) 1998-01-15
DE69128319T2 DE69128319T2 (de) 1998-07-09

Family

ID=10681445

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128319T Expired - Fee Related DE69128319T2 (de) 1990-08-31 1991-08-30 Arbeitsplatz mit Stossbetriebdatenübertragung

Country Status (5)

Country Link
US (1) US5440754A (de)
EP (1) EP0473455B1 (de)
JP (1) JPH06202985A (de)
DE (1) DE69128319T2 (de)
GB (1) GB9019023D0 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630163A (en) * 1991-08-09 1997-05-13 Vadem Corporation Computer having a single bus supporting multiple bus architectures operating with different bus parameters
US5467295A (en) * 1992-04-30 1995-11-14 Intel Corporation Bus arbitration with master unit controlling bus and locking a slave unit that can relinquish bus for other masters while maintaining lock on slave unit
TW276312B (de) * 1992-10-20 1996-05-21 Cirrlis Logic Inc
US5631853A (en) * 1995-11-13 1997-05-20 Motorola Inc. Flexible configuration of timebases in a timer system
US5963721A (en) * 1995-12-29 1999-10-05 Texas Instruments Incorporated Microprocessor system with capability for asynchronous bus transactions
JP3934710B2 (ja) * 1996-09-13 2007-06-20 株式会社ルネサステクノロジ マイクロプロセッサ
US6535519B1 (en) 1998-08-28 2003-03-18 Lsi Logic Corporation Method and apparatus for data sharing between two different blocks in an integrated circuit
US6256697B1 (en) * 1998-12-30 2001-07-03 Intel Corporation Method and apparatus for reusing arbitration signals to frame data transfers between hub agents

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3584690D1 (de) * 1984-06-20 1992-01-02 Convex Computer Corp Ein-/ausgabebus fuer rechner.
US4851990A (en) * 1987-02-09 1989-07-25 Advanced Micro Devices, Inc. High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
US4858116A (en) * 1987-05-01 1989-08-15 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
DE3779313D1 (de) * 1987-08-20 1992-06-25 Ibm Schnittstellenmechanismus fuer informationsuebertragungssteuerung zwischen zwei vorrichtungen.
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design
US5029124A (en) * 1988-05-17 1991-07-02 Digital Equipment Corporation Method and apparatus for providing high speed parallel transfer of bursts of data
EP0425550B1 (de) * 1988-06-30 1995-01-04 Wang Laboratories, Inc. Steuereinheit für den speicher
US5051985A (en) * 1988-10-28 1991-09-24 International Business Machines Corporation Contention resolution in a communications ring
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5237670A (en) * 1989-01-30 1993-08-17 Alantec, Inc. Method and apparatus for data transfer between source and destination modules
US5191657A (en) * 1989-11-09 1993-03-02 Ast Research, Inc. Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus
US5159672A (en) * 1989-12-28 1992-10-27 Intel Corporation Burst EPROM architecture
US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
US5237567A (en) * 1990-10-31 1993-08-17 Control Data Systems, Inc. Processor communication bus
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus

Also Published As

Publication number Publication date
EP0473455B1 (de) 1997-12-03
JPH06202985A (ja) 1994-07-22
GB9019023D0 (en) 1990-10-17
EP0473455A2 (de) 1992-03-04
EP0473455A3 (en) 1993-11-24
DE69128319T2 (de) 1998-07-09
US5440754A (en) 1995-08-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN

8339 Ceased/non-payment of the annual fee