DE69114531T2 - Löten von Wafern unter Verwendung von eingeschlossenem oxydierendem Dampf. - Google Patents

Löten von Wafern unter Verwendung von eingeschlossenem oxydierendem Dampf.

Info

Publication number
DE69114531T2
DE69114531T2 DE69114531T DE69114531T DE69114531T2 DE 69114531 T2 DE69114531 T2 DE 69114531T2 DE 69114531 T DE69114531 T DE 69114531T DE 69114531 T DE69114531 T DE 69114531T DE 69114531 T2 DE69114531 T2 DE 69114531T2
Authority
DE
Germany
Prior art keywords
wafers
soldering
trapped
oxidizing steam
oxidizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69114531T
Other languages
English (en)
Other versions
DE69114531D1 (de
Inventor
John Preston Short
Craig James Mclachlan
George Vernon Rouse
James Robert Zibrida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harris Corp
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23891385&utm_source=***_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69114531(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Harris Corp filed Critical Harris Corp
Publication of DE69114531D1 publication Critical patent/DE69114531D1/de
Application granted granted Critical
Publication of DE69114531T2 publication Critical patent/DE69114531T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE69114531T 1990-02-07 1991-02-02 Löten von Wafern unter Verwendung von eingeschlossenem oxydierendem Dampf. Expired - Lifetime DE69114531T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US47632290A 1990-02-07 1990-02-07

Publications (2)

Publication Number Publication Date
DE69114531D1 DE69114531D1 (de) 1995-12-21
DE69114531T2 true DE69114531T2 (de) 1996-04-25

Family

ID=23891385

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114531T Expired - Lifetime DE69114531T2 (de) 1990-02-07 1991-02-02 Löten von Wafern unter Verwendung von eingeschlossenem oxydierendem Dampf.

Country Status (3)

Country Link
EP (1) EP0441270B1 (de)
JP (1) JP2992843B2 (de)
DE (1) DE69114531T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5849627A (en) * 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
US6909146B1 (en) 1992-02-12 2005-06-21 Intersil Corporation Bonded wafer with metal silicidation
JPH06244389A (ja) * 1992-12-25 1994-09-02 Canon Inc 半導体基板の作製方法及び該方法により作製された半導体基板
WO1994023444A2 (en) * 1993-04-02 1994-10-13 Harris Corporation Bonded wafer processing with oxidative bonding
JPH11307747A (ja) * 1998-04-17 1999-11-05 Nec Corp Ｓｏｉ基板およびその製造方法
JP5055671B2 (ja) * 2001-07-26 2012-10-24 信越半導体株式会社 Ｓｏｉ基板の製造方法
AU2002307578A1 (en) 2002-04-30 2003-12-02 Agency For Science Technology And Research A method of wafer/substrate bonding
US7259466B2 (en) 2002-12-17 2007-08-21 Finisar Corporation Low temperature bonding of multilayer substrates
US7361593B2 (en) 2002-12-17 2008-04-22 Finisar Corporation Methods of forming vias in multilayer substrates
FR2919958B1 (fr) * 2007-08-07 2009-12-18 Commissariat Energie Atomique Procede de report d'une couche sur un materiau liquide
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL281360A (de) * 1961-07-26 1900-01-01
JPS6051700A (ja) * 1983-08-31 1985-03-23 Toshiba Corp シリコン結晶体の接合方法

Also Published As

Publication number Publication date
JP2992843B2 (ja) 1999-12-20
DE69114531D1 (de) 1995-12-21
EP0441270B1 (de) 1995-11-15
EP0441270A2 (de) 1991-08-14
EP0441270A3 (en) 1992-11-19
JPH05326896A (ja) 1993-12-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition