DE69026565D1 - Verfahren zur Herstellung einer halbleiterintegrierten Schaltung umfassend einen Heteroübergang-Bipolartransistor und/oder einen vergrabenen Widerstand - Google Patents

Verfahren zur Herstellung einer halbleiterintegrierten Schaltung umfassend einen Heteroübergang-Bipolartransistor und/oder einen vergrabenen Widerstand

Info

Publication number
DE69026565D1
DE69026565D1 DE69026565T DE69026565T DE69026565D1 DE 69026565 D1 DE69026565 D1 DE 69026565D1 DE 69026565 T DE69026565 T DE 69026565T DE 69026565 T DE69026565 T DE 69026565T DE 69026565 D1 DE69026565 D1 DE 69026565D1
Authority
DE
Germany
Prior art keywords
manufacturing
integrated circuit
semiconductor integrated
bipolar transistor
heterojunction bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69026565T
Other languages
English (en)
Other versions
DE69026565T2 (de
Inventor
Claudine Villalon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Application granted granted Critical
Publication of DE69026565D1 publication Critical patent/DE69026565D1/de
Publication of DE69026565T2 publication Critical patent/DE69026565T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/6631Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318Heterojunction transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/011Bipolar transistors
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/072Heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
DE69026565T 1989-09-21 1990-09-17 Verfahren zur Herstellung einer halbleiterintegrierten Schaltung umfassend einen Heteroübergang-Bipolartransistor und/oder einen vergrabenen Widerstand Expired - Fee Related DE69026565T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8912405A FR2652200A1 (fr) 1989-09-21 1989-09-21 Procede de realisation d'un circuit semiconducteur integre incluant un transistor bipolaire a heterojonction et/ou des resistances enterrees.

Publications (2)

Publication Number Publication Date
DE69026565D1 true DE69026565D1 (de) 1996-05-23
DE69026565T2 DE69026565T2 (de) 1996-11-07

Family

ID=9385727

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69026565T Expired - Fee Related DE69026565T2 (de) 1989-09-21 1990-09-17 Verfahren zur Herstellung einer halbleiterintegrierten Schaltung umfassend einen Heteroübergang-Bipolartransistor und/oder einen vergrabenen Widerstand

Country Status (5)

Country Link
US (1) US5073508A (de)
EP (1) EP0420322B1 (de)
JP (1) JPH03142970A (de)
DE (1) DE69026565T2 (de)
FR (1) FR2652200A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168071A (en) * 1991-04-05 1992-12-01 At&T Bell Laboratories Method of making semiconductor devices
JPH0582560A (ja) * 1991-09-20 1993-04-02 Sony Corp 電界効果型トランジスタの製造方法
JPH0669227A (ja) * 1992-05-29 1994-03-11 Texas Instr Inc <Ti> 化合物半導体のヘテロ接合バイポーラトランジスタ及びその製造方法
US5286661A (en) * 1992-08-26 1994-02-15 Motorola, Inc. Method of forming a bipolar transistor having an emitter overhang
US5883566A (en) * 1997-02-24 1999-03-16 International Business Machines Corporation Noise-isolated buried resistor
DE19842106A1 (de) * 1998-09-08 2000-03-09 Inst Halbleiterphysik Gmbh Vertikaler Bipolartransistor und Verfahren zu seiner Herstellung
US7300595B2 (en) * 2003-12-25 2007-11-27 Tdk Corporation Method for filling concave portions of concavo-convex pattern and method for manufacturing magnetic recording medium

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617724A (en) * 1983-06-30 1986-10-21 Fujitsu Limited Process for fabricating heterojunction bipolar transistor with low base resistance
JPS61147571A (ja) * 1984-12-21 1986-07-05 Toshiba Corp ヘテロ接合バイポ−ラトランジスタの製造方法
JPS63276267A (ja) * 1987-05-08 1988-11-14 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
US5073508A (en) 1991-12-17
JPH03142970A (ja) 1991-06-18
EP0420322B1 (de) 1996-04-17
DE69026565T2 (de) 1996-11-07
FR2652200A1 (fr) 1991-03-22
EP0420322A1 (de) 1991-04-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee