DE68920560D1 - Restprüfungsvorrichtung zur Fehlerkennung in Additions-, Substraktions-, Multiplikations-, Divisions- und Quadratwurzel-Operationen. - Google Patents
Restprüfungsvorrichtung zur Fehlerkennung in Additions-, Substraktions-, Multiplikations-, Divisions- und Quadratwurzel-Operationen.Info
- Publication number
- DE68920560D1 DE68920560D1 DE68920560T DE68920560T DE68920560D1 DE 68920560 D1 DE68920560 D1 DE 68920560D1 DE 68920560 T DE68920560 T DE 68920560T DE 68920560 T DE68920560 T DE 68920560T DE 68920560 D1 DE68920560 D1 DE 68920560D1
- Authority
- DE
- Germany
- Prior art keywords
- subtraction
- multiplication
- division
- addition
- error detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
- Measurement Of Resistance Or Impedance (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/276,200 US4926374A (en) | 1988-11-23 | 1988-11-23 | Residue checking apparatus for detecting errors in add, subtract, multiply, divide and square root operations |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68920560D1 true DE68920560D1 (de) | 1995-02-23 |
DE68920560T2 DE68920560T2 (de) | 1995-07-13 |
Family
ID=23055617
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68920560T Expired - Fee Related DE68920560T2 (de) | 1988-11-23 | 1989-10-21 | Restprüfungsvorrichtung zur Fehlerkennung in Additions-, Substraktions-, Multiplikations-, Divisions- und Quadratwurzel-Operationen. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4926374A (de) |
EP (1) | EP0374420B1 (de) |
JP (1) | JPH0618040B2 (de) |
DE (1) | DE68920560T2 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5081629A (en) * | 1989-05-08 | 1992-01-14 | Unisys Corporation | Fault isolation for multiphase clock signals supplied to dual modules which are checked by comparison using residue code generators |
US5253349A (en) * | 1991-01-30 | 1993-10-12 | International Business Machines Corporation | Decreasing processing time for type 1 dyadic instructions |
US5794025A (en) * | 1996-05-09 | 1998-08-11 | Maker Communications, Inc. | Method and device for performing modulo-based arithmetic operations in an asynchronous transfer mode cell processing system |
US6128303A (en) | 1996-05-09 | 2000-10-03 | Maker Communications, Inc. | Asynchronous transfer mode cell processing system with scoreboard scheduling |
US5748631A (en) * | 1996-05-09 | 1998-05-05 | Maker Communications, Inc. | Asynchronous transfer mode cell processing system with multiple cell source multiplexing |
US5748630A (en) * | 1996-05-09 | 1998-05-05 | Maker Communications, Inc. | Asynchronous transfer mode cell processing system with load multiple instruction and memory write-back |
JP4317212B2 (ja) | 2003-03-20 | 2009-08-19 | アーム・リミテッド | 集積回路の処理段における系統的及び確率的誤り検出及び復旧 |
WO2004084233A1 (en) | 2003-03-20 | 2004-09-30 | Arm Limited | Momory system having fast and slow data reading mechanisms |
US8185812B2 (en) | 2003-03-20 | 2012-05-22 | Arm Limited | Single event upset error detection within an integrated circuit |
US8650470B2 (en) | 2003-03-20 | 2014-02-11 | Arm Limited | Error recovery within integrated circuit |
US7278080B2 (en) | 2003-03-20 | 2007-10-02 | Arm Limited | Error detection and recovery within processing stages of an integrated circuit |
WO2005124578A2 (en) * | 2004-06-16 | 2005-12-29 | Discretix Technologies Ltd | System, method and apparatus of error detection during a modular operation |
GB2456624B (en) * | 2008-01-16 | 2012-05-30 | Ibm | Method and apparatus for residue modulo checking for arithmetic operations |
US8171386B2 (en) | 2008-03-27 | 2012-05-01 | Arm Limited | Single event upset error detection within sequential storage circuitry of an integrated circuit |
US8161367B2 (en) | 2008-10-07 | 2012-04-17 | Arm Limited | Correction of single event upset error within sequential storage circuitry of an integrated circuit |
US8566383B2 (en) * | 2008-10-17 | 2013-10-22 | International Business Machines Corporation | Distributed residue-checking of a floating point unit |
EP2438511B1 (de) | 2010-03-22 | 2019-07-03 | LRDC Systems, LLC | Verfahren zur identifikation und zum schutz der integrität eines satzes von quelldaten |
US8493120B2 (en) | 2011-03-10 | 2013-07-23 | Arm Limited | Storage circuitry and method with increased resilience to single event upsets |
US9110768B2 (en) * | 2012-12-28 | 2015-08-18 | Intel Corporation | Residue based error detection for integer and floating point execution units |
US10303440B2 (en) | 2017-01-19 | 2019-05-28 | International Business Machines Corporation | Combined residue circuit protecting binary and decimal data |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3227865A (en) * | 1962-06-29 | 1966-01-04 | Ibm | Residue checking system |
US3624373A (en) * | 1969-12-16 | 1971-11-30 | Bell Telephone Labor Inc | Apparatus for performing and checking logical operations |
US3659089A (en) * | 1970-12-23 | 1972-04-25 | Ibm | Error detecting and correcting system and method |
US3699323A (en) * | 1970-12-23 | 1972-10-17 | Ibm | Error detecting and correcting system and method |
US3816728A (en) * | 1972-12-14 | 1974-06-11 | Ibm | Modulo 9 residue generating and checking circuit |
US3814923A (en) * | 1973-01-02 | 1974-06-04 | Bell Telephone Labor Inc | Error detection system |
-
1988
- 1988-11-23 US US07/276,200 patent/US4926374A/en not_active Expired - Fee Related
-
1989
- 1989-09-13 JP JP1235844A patent/JPH0618040B2/ja not_active Expired - Lifetime
- 1989-10-21 DE DE68920560T patent/DE68920560T2/de not_active Expired - Fee Related
- 1989-10-21 EP EP89119567A patent/EP0374420B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02150921A (ja) | 1990-06-11 |
US4926374A (en) | 1990-05-15 |
EP0374420A2 (de) | 1990-06-27 |
DE68920560T2 (de) | 1995-07-13 |
JPH0618040B2 (ja) | 1994-03-09 |
EP0374420B1 (de) | 1995-01-11 |
EP0374420A3 (de) | 1991-01-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |