DE68919459D1 - Schaltung zur Unterdrückung von Störsignalen. - Google Patents
Schaltung zur Unterdrückung von Störsignalen.Info
- Publication number
- DE68919459D1 DE68919459D1 DE68919459T DE68919459T DE68919459D1 DE 68919459 D1 DE68919459 D1 DE 68919459D1 DE 68919459 T DE68919459 T DE 68919459T DE 68919459 T DE68919459 T DE 68919459T DE 68919459 D1 DE68919459 D1 DE 68919459D1
- Authority
- DE
- Germany
- Prior art keywords
- interference suppression
- suppression circuit
- interference
- circuit
- suppression
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US24519788A | 1988-09-16 | 1988-09-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68919459D1 true DE68919459D1 (de) | 1995-01-05 |
DE68919459T2 DE68919459T2 (de) | 1995-03-30 |
Family
ID=22925701
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68919459T Expired - Fee Related DE68919459T2 (de) | 1988-09-16 | 1989-09-15 | Schaltung zur Unterdrückung von Störsignalen. |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0361233B1 (de) |
JP (1) | JP3077808B2 (de) |
KR (1) | KR0150632B1 (de) |
DE (1) | DE68919459T2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0463243B1 (de) * | 1990-06-29 | 1997-04-23 | Koninklijke Philips Electronics N.V. | Integrierte Halbleiterschaltung mit einem Detektor |
US5235602A (en) * | 1991-06-11 | 1993-08-10 | International Business Machines Corporation | Synchronous/asynchronous i/o channel check and parity check detector |
US6718523B2 (en) | 2001-07-05 | 2004-04-06 | International Business Machines Corporation | Reduced pessimism clock gating tests for a timing analysis tool |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4337525A (en) * | 1979-04-17 | 1982-06-29 | Nippon Electric Co., Ltd. | Asynchronous circuit responsive to changes in logic level |
JPS5963094A (ja) * | 1982-10-04 | 1984-04-10 | Fujitsu Ltd | メモリ装置 |
-
1989
- 1989-09-12 KR KR1019890013258A patent/KR0150632B1/ko not_active IP Right Cessation
- 1989-09-14 JP JP01237406A patent/JP3077808B2/ja not_active Expired - Fee Related
- 1989-09-15 DE DE68919459T patent/DE68919459T2/de not_active Expired - Fee Related
- 1989-09-15 EP EP89117106A patent/EP0361233B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0361233A3 (en) | 1990-06-20 |
JP3077808B2 (ja) | 2000-08-21 |
EP0361233B1 (de) | 1994-11-23 |
JPH02210914A (ja) | 1990-08-22 |
KR0150632B1 (ko) | 1998-12-01 |
EP0361233A2 (de) | 1990-04-04 |
DE68919459T2 (de) | 1995-03-30 |
KR900005475A (ko) | 1990-04-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |