DE60324762D1 - Anordnung und Verfahren zur Zuteilung und Initialisierung einer Cachespeicherzeile - Google Patents
Anordnung und Verfahren zur Zuteilung und Initialisierung einer CachespeicherzeileInfo
- Publication number
- DE60324762D1 DE60324762D1 DE60324762T DE60324762T DE60324762D1 DE 60324762 D1 DE60324762 D1 DE 60324762D1 DE 60324762 T DE60324762 T DE 60324762T DE 60324762 T DE60324762 T DE 60324762T DE 60324762 D1 DE60324762 D1 DE 60324762D1
- Authority
- DE
- Germany
- Prior art keywords
- initializing
- allocating
- arrangement
- cache line
- cache
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6028—Prefetching based on hints or prefetch instructions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/364,920 US7080211B2 (en) | 2002-02-12 | 2003-02-11 | Microprocessor apparatus and method for prefetch, allocation, and initialization of a cache line from memory |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60324762D1 true DE60324762D1 (de) | 2009-01-02 |
Family
ID=32681699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60324762T Expired - Lifetime DE60324762D1 (de) | 2003-02-11 | 2003-06-04 | Anordnung und Verfahren zur Zuteilung und Initialisierung einer Cachespeicherzeile |
Country Status (5)
Country | Link |
---|---|
US (1) | US7080211B2 (de) |
EP (1) | EP1447743B1 (de) |
CN (1) | CN1225690C (de) |
DE (1) | DE60324762D1 (de) |
TW (1) | TWI220223B (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7089371B2 (en) * | 2002-02-12 | 2006-08-08 | Ip-First, Llc | Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory |
US7111125B2 (en) * | 2002-04-02 | 2006-09-19 | Ip-First, Llc | Apparatus and method for renaming a data block within a cache |
US7188215B2 (en) | 2003-06-19 | 2007-03-06 | Ip-First, Llc | Apparatus and method for renaming a cache line |
US8041896B2 (en) * | 2008-04-30 | 2011-10-18 | Hewlett-Packard Development Company, L.P. | Virtualization platform with dedicated cache access |
US8533437B2 (en) * | 2009-06-01 | 2013-09-10 | Via Technologies, Inc. | Guaranteed prefetch instruction |
CN101916181B (zh) * | 2009-08-28 | 2014-04-23 | 威盛电子股份有限公司 | 微处理器及其执行方法 |
US8595471B2 (en) * | 2010-01-22 | 2013-11-26 | Via Technologies, Inc. | Executing repeat load string instruction with guaranteed prefetch microcode to prefetch into cache for loading up to the last value in architectural register |
US8856453B2 (en) | 2012-03-01 | 2014-10-07 | International Business Machines Corporation | Persistent prefetch data stream settings |
US9811467B2 (en) * | 2014-02-03 | 2017-11-07 | Cavium, Inc. | Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor |
US10761925B2 (en) * | 2015-03-24 | 2020-09-01 | Nxp Usa, Inc. | Multi-channel network-on-a-chip |
US11157407B2 (en) * | 2016-12-15 | 2021-10-26 | Optimum Semiconductor Technologies Inc. | Implementing atomic primitives using cache line locking |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4959777A (en) | 1987-07-27 | 1990-09-25 | Motorola Computer X | Write-shared cache circuit for multiprocessor system |
CA2051209C (en) | 1990-11-30 | 1996-05-07 | Pradeep S. Sindhu | Consistency protocols for shared memory multiprocessors |
JP2500101B2 (ja) | 1992-12-18 | 1996-05-29 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 共用変数の値を更新する方法 |
US5903911A (en) | 1993-06-22 | 1999-05-11 | Dell Usa, L.P. | Cache-based computer system employing memory control circuit and method for write allocation and data prefetch |
US5892970A (en) | 1996-07-01 | 1999-04-06 | Sun Microsystems, Inc. | Multiprocessing system configured to perform efficient block copy operations |
EP0825538A1 (de) | 1996-08-16 | 1998-02-25 | Lsi Logic Corporation | Cachespeichersystem |
JP2916421B2 (ja) | 1996-09-09 | 1999-07-05 | 株式会社東芝 | キャッシュフラッシュ装置およびデータ処理方法 |
US5966734A (en) | 1996-10-18 | 1999-10-12 | Samsung Electronics Co., Ltd. | Resizable and relocatable memory scratch pad as a cache slice |
US6018763A (en) | 1997-05-28 | 2000-01-25 | 3Com Corporation | High performance shared memory for a bridge router supporting cache coherency |
US5944815A (en) | 1998-01-12 | 1999-08-31 | Advanced Micro Devices, Inc. | Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access |
US6014735A (en) | 1998-03-31 | 2000-01-11 | Intel Corporation | Instruction set extension using prefixes |
US6088789A (en) | 1998-05-13 | 2000-07-11 | Advanced Micro Devices, Inc. | Prefetch instruction specifying destination functional unit and read/write access mode |
US6253306B1 (en) * | 1998-07-29 | 2001-06-26 | Advanced Micro Devices, Inc. | Prefetch instruction mechanism for processor |
US6289420B1 (en) | 1999-05-06 | 2001-09-11 | Sun Microsystems, Inc. | System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem |
US6266744B1 (en) | 1999-05-18 | 2001-07-24 | Advanced Micro Devices, Inc. | Store to load forwarding using a dependency link file |
US6470444B1 (en) | 1999-06-16 | 2002-10-22 | Intel Corporation | Method and apparatus for dividing a store operation into pre-fetch and store micro-operations |
US6557084B2 (en) | 1999-07-13 | 2003-04-29 | International Business Machines Corporation | Apparatus and method to improve performance of reads from and writes to shared memory locations |
US6460132B1 (en) | 1999-08-31 | 2002-10-01 | Advanced Micro Devices, Inc. | Massively parallel instruction predecoding |
JP2001222466A (ja) | 2000-02-10 | 2001-08-17 | Nec Corp | マルチプロセッサ・システムと共有メモリ制御システム及び方法並びに記録媒体 |
US6751710B2 (en) | 2000-06-10 | 2004-06-15 | Hewlett-Packard Development Company, L.P. | Scalable multiprocessor system and cache coherence method |
US6845008B2 (en) | 2001-03-30 | 2005-01-18 | Intel Corporation | Docking station to cool a notebook computer |
US6915415B2 (en) | 2002-01-07 | 2005-07-05 | International Business Machines Corporation | Method and apparatus for mapping software prefetch instructions to hardware prefetch logic |
US7380103B2 (en) | 2002-04-02 | 2008-05-27 | Ip-First, Llc | Apparatus and method for selective control of results write back |
US6832296B2 (en) | 2002-04-09 | 2004-12-14 | Ip-First, Llc | Microprocessor with repeat prefetch instruction |
-
2003
- 2003-02-11 US US10/364,920 patent/US7080211B2/en not_active Expired - Lifetime
- 2003-06-04 EP EP03253502A patent/EP1447743B1/de not_active Expired - Lifetime
- 2003-06-04 DE DE60324762T patent/DE60324762D1/de not_active Expired - Lifetime
- 2003-06-13 TW TW092116036A patent/TWI220223B/zh not_active IP Right Cessation
- 2003-08-05 CN CNB031526632A patent/CN1225690C/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1225690C (zh) | 2005-11-02 |
TWI220223B (en) | 2004-08-11 |
TW200415514A (en) | 2004-08-16 |
EP1447743A3 (de) | 2004-11-10 |
EP1447743A2 (de) | 2004-08-18 |
CN1487410A (zh) | 2004-04-07 |
US20040158680A1 (en) | 2004-08-12 |
US7080211B2 (en) | 2006-07-18 |
EP1447743B1 (de) | 2008-11-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |