DE60315952D1 - PROCEDURE AND ARRANGEMENT FOR AN ADDITIONAL CONTROL BUS IN A COMPUTER SYSTEM - Google Patents
PROCEDURE AND ARRANGEMENT FOR AN ADDITIONAL CONTROL BUS IN A COMPUTER SYSTEMInfo
- Publication number
- DE60315952D1 DE60315952D1 DE60315952T DE60315952T DE60315952D1 DE 60315952 D1 DE60315952 D1 DE 60315952D1 DE 60315952 T DE60315952 T DE 60315952T DE 60315952 T DE60315952 T DE 60315952T DE 60315952 D1 DE60315952 D1 DE 60315952D1
- Authority
- DE
- Germany
- Prior art keywords
- procedure
- arrangement
- computer system
- control bus
- additional control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
- Selective Calling Equipment (AREA)
- Hardware Redundancy (AREA)
- Memory System (AREA)
- Debugging And Monitoring (AREA)
Abstract
An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command interface. The memory communicates with other components in the system via a main command bus configured to transfer address-specific commands and a supplementary command bus configured to transfer general commands. Commands may be received by the memory simultaneously at the respective interfaces.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/073,740 US6728150B2 (en) | 2002-02-11 | 2002-02-11 | Method and apparatus for supplementary command bus |
PCT/US2003/002610 WO2003069484A2 (en) | 2002-02-11 | 2003-01-29 | Method and apparatus for supplementary command bus in a computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60315952D1 true DE60315952D1 (en) | 2007-10-11 |
Family
ID=27659749
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60315952T Expired - Lifetime DE60315952D1 (en) | 2002-02-11 | 2003-01-29 | PROCEDURE AND ARRANGEMENT FOR AN ADDITIONAL CONTROL BUS IN A COMPUTER SYSTEM |
Country Status (11)
Country | Link |
---|---|
US (3) | US6728150B2 (en) |
EP (1) | EP1474749B1 (en) |
JP (2) | JP4034268B2 (en) |
KR (1) | KR100647443B1 (en) |
CN (1) | CN100363917C (en) |
AT (1) | ATE371899T1 (en) |
AU (1) | AU2003209422A1 (en) |
DE (1) | DE60315952D1 (en) |
DK (1) | DK1474749T3 (en) |
TW (1) | TWI241519B (en) |
WO (1) | WO2003069484A2 (en) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6798711B2 (en) * | 2002-03-19 | 2004-09-28 | Micron Technology, Inc. | Memory with address management |
US8250295B2 (en) | 2004-01-05 | 2012-08-21 | Smart Modular Technologies, Inc. | Multi-rank memory module that emulates a memory module having a different number of ranks |
US7916574B1 (en) | 2004-03-05 | 2011-03-29 | Netlist, Inc. | Circuit providing load isolation and memory domain translation for memory module |
US7532537B2 (en) | 2004-03-05 | 2009-05-12 | Netlist, Inc. | Memory module with a circuit providing load isolation and memory domain translation |
US7289386B2 (en) | 2004-03-05 | 2007-10-30 | Netlist, Inc. | Memory module decoder |
US7454586B2 (en) * | 2005-03-30 | 2008-11-18 | Intel Corporation | Memory device commands |
TWI254960B (en) * | 2005-07-01 | 2006-05-11 | Chunghwa Picture Tubes Ltd | Plasma display device |
US7966446B2 (en) * | 2005-09-12 | 2011-06-21 | Samsung Electronics Co., Ltd. | Memory system and method having point-to-point link |
US8045416B2 (en) * | 2008-03-05 | 2011-10-25 | Micron Technology, Inc. | Method and memory device providing reduced quantity of interconnections |
US8154901B1 (en) | 2008-04-14 | 2012-04-10 | Netlist, Inc. | Circuit providing load isolation and noise reduction |
US9128632B2 (en) | 2009-07-16 | 2015-09-08 | Netlist, Inc. | Memory module with distributed data buffers and method of operation |
AU2010201718B2 (en) * | 2010-04-29 | 2012-08-23 | Canon Kabushiki Kaisha | Method, system and apparatus for identifying a cache line |
US20120272013A1 (en) * | 2011-04-25 | 2012-10-25 | Ming-Shi Liou | Data access system with at least multiple configurable chip select signals transmitted to different memory ranks and related data access method thereof |
US20120278527A1 (en) * | 2011-04-26 | 2012-11-01 | Byungcheol Cho | System architecture based on hybrid raid storage |
US9176670B2 (en) * | 2011-04-26 | 2015-11-03 | Taejin Info Tech Co., Ltd. | System architecture based on asymmetric raid storage |
US8719523B2 (en) * | 2011-10-03 | 2014-05-06 | International Business Machines Corporation | Maintaining multiple target copies |
KR20160038034A (en) | 2013-07-27 | 2016-04-06 | 넷리스트 인코포레이티드 | Memory module with local synchronization |
KR20200126678A (en) | 2019-04-30 | 2020-11-09 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
US11139010B2 (en) | 2018-12-11 | 2021-10-05 | SK Hynix Inc. | Memory system and operating method of the memory system |
KR20200126666A (en) * | 2019-04-30 | 2020-11-09 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
US11404097B2 (en) | 2018-12-11 | 2022-08-02 | SK Hynix Inc. | Memory system and operating method of the memory system |
KR20200124045A (en) | 2019-04-23 | 2020-11-02 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
KR20200137548A (en) | 2019-05-30 | 2020-12-09 | 에스케이하이닉스 주식회사 | Memory device and test operating method thereof |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
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US1173773A (en) * | 1913-04-05 | 1916-02-29 | Cook Frank B Co | Telephony. |
US4426644A (en) * | 1980-09-12 | 1984-01-17 | Siemens Ag | Method and apparatus for generating three coordinate signals x, y, z for an x, y, z display device |
IL97315A (en) * | 1990-02-28 | 1994-10-07 | Hughes Aircraft Co | Multiple cluster signal processor |
US5369651A (en) * | 1992-06-30 | 1994-11-29 | Intel Corporation | Multiplexed byte enable bus for partial word writes to ECC protected memory |
US5319753A (en) * | 1992-09-29 | 1994-06-07 | Zilog, Inc. | Queued interrupt mechanism with supplementary command/status/message information |
US5721860A (en) * | 1994-05-24 | 1998-02-24 | Intel Corporation | Memory controller for independently supporting synchronous and asynchronous DRAM memories |
DE69513113T2 (en) * | 1994-08-31 | 2000-06-21 | Motorola Inc | Synchronous memory access method |
US5600605A (en) | 1995-06-07 | 1997-02-04 | Micron Technology, Inc. | Auto-activate on synchronous dynamic random access memory |
JPH0973776A (en) * | 1995-09-07 | 1997-03-18 | Mitsubishi Electric Corp | Synchronous semiconductor memory |
US5748551A (en) * | 1995-12-29 | 1998-05-05 | Micron Technology, Inc. | Memory device with multiple internal banks and staggered command execution |
JPH09311812A (en) * | 1996-05-24 | 1997-12-02 | Oki Electric Ind Co Ltd | Microcomputer |
US6230235B1 (en) * | 1996-08-08 | 2001-05-08 | Apache Systems, Inc. | Address lookup DRAM aging |
US6067255A (en) * | 1997-07-03 | 2000-05-23 | Samsung Electronics Co., Ltd. | Merged memory and logic (MML) integrated circuits including independent memory bank signals and methods |
US6260127B1 (en) * | 1998-07-13 | 2001-07-10 | Compaq Computer Corporation | Method and apparatus for supporting heterogeneous memory in computer systems |
FI982374A (en) | 1998-11-02 | 2000-06-21 | Nokia Mobile Phones Ltd | memory Interface |
US6449679B2 (en) * | 1999-02-26 | 2002-09-10 | Micron Technology, Inc. | RAM controller interface device for RAM compatibility (memory translator hub) |
JP2000268564A (en) | 1999-03-16 | 2000-09-29 | Nec Eng Ltd | Synchronous dram |
JP4034923B2 (en) * | 1999-05-07 | 2008-01-16 | 富士通株式会社 | Semiconductor memory device operation control method and semiconductor memory device |
JP3871853B2 (en) * | 2000-05-26 | 2007-01-24 | 株式会社ルネサステクノロジ | Semiconductor device and operation method thereof |
US6549991B1 (en) * | 2000-08-31 | 2003-04-15 | Silicon Integrated Systems Corp. | Pipelined SDRAM memory controller to optimize bus utilization |
JP2002108691A (en) * | 2000-09-29 | 2002-04-12 | Mitsubishi Electric Corp | Semiconductor memory and method for controlling the same device |
US6553449B1 (en) * | 2000-09-29 | 2003-04-22 | Intel Corporation | System and method for providing concurrent row and column commands |
US6732305B2 (en) * | 2000-10-05 | 2004-05-04 | United Memories, Inc. | Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry |
US6676028B2 (en) * | 2001-04-23 | 2004-01-13 | Howard Jacobson | Electrical resistance foot warmer for use with a motor vehicle |
JP2004213337A (en) * | 2002-12-27 | 2004-07-29 | Nec Computertechno Ltd | Semiconductor storage device and mounting type semiconductor device |
US7558933B2 (en) * | 2003-12-24 | 2009-07-07 | Ati Technologies Inc. | Synchronous dynamic random access memory interface and method |
-
2002
- 2002-02-11 US US10/073,740 patent/US6728150B2/en not_active Expired - Lifetime
-
2003
- 2003-01-29 EP EP03707583A patent/EP1474749B1/en not_active Expired - Lifetime
- 2003-01-29 AU AU2003209422A patent/AU2003209422A1/en not_active Abandoned
- 2003-01-29 AT AT03707583T patent/ATE371899T1/en not_active IP Right Cessation
- 2003-01-29 JP JP2003568540A patent/JP4034268B2/en not_active Expired - Lifetime
- 2003-01-29 DE DE60315952T patent/DE60315952D1/en not_active Expired - Lifetime
- 2003-01-29 WO PCT/US2003/002610 patent/WO2003069484A2/en active IP Right Grant
- 2003-01-29 DK DK03707583T patent/DK1474749T3/en active
- 2003-01-29 CN CNB038037181A patent/CN100363917C/en not_active Expired - Lifetime
- 2003-01-29 KR KR1020047012396A patent/KR100647443B1/en active IP Right Grant
- 2003-01-30 TW TW092102144A patent/TWI241519B/en not_active IP Right Cessation
-
2004
- 2004-03-23 US US10/708,751 patent/US6876589B2/en not_active Expired - Lifetime
- 2004-11-30 US US10/904,811 patent/US7339838B2/en not_active Expired - Lifetime
-
2007
- 2007-01-22 JP JP2007012054A patent/JP2007102823A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
WO2003069484A3 (en) | 2003-12-18 |
US6876589B2 (en) | 2005-04-05 |
JP2005518017A (en) | 2005-06-16 |
TWI241519B (en) | 2005-10-11 |
US20050088902A1 (en) | 2005-04-28 |
JP4034268B2 (en) | 2008-01-16 |
KR20040081197A (en) | 2004-09-20 |
EP1474749A2 (en) | 2004-11-10 |
US7339838B2 (en) | 2008-03-04 |
US20040170071A1 (en) | 2004-09-02 |
DK1474749T3 (en) | 2007-12-03 |
WO2003069484A2 (en) | 2003-08-21 |
AU2003209422A1 (en) | 2003-09-04 |
JP2007102823A (en) | 2007-04-19 |
US6728150B2 (en) | 2004-04-27 |
TW200304087A (en) | 2003-09-16 |
US20030151963A1 (en) | 2003-08-14 |
ATE371899T1 (en) | 2007-09-15 |
CN1630858A (en) | 2005-06-22 |
CN100363917C (en) | 2008-01-23 |
AU2003209422A8 (en) | 2003-09-04 |
EP1474749B1 (en) | 2007-08-29 |
KR100647443B1 (en) | 2006-11-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |