DE60235740D1 - Verfahren und Vorrichtung zur Verzögerungsanpassun - Google Patents

Verfahren und Vorrichtung zur Verzögerungsanpassun

Info

Publication number
DE60235740D1
DE60235740D1 DE60235740T DE60235740T DE60235740D1 DE 60235740 D1 DE60235740 D1 DE 60235740D1 DE 60235740 T DE60235740 T DE 60235740T DE 60235740 T DE60235740 T DE 60235740T DE 60235740 D1 DE60235740 D1 DE 60235740D1
Authority
DE
Germany
Prior art keywords
clock signal
divided clock
transition delay
transition
delay adjustment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60235740T
Other languages
English (en)
Inventor
Kwang Y Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of DE60235740D1 publication Critical patent/DE60235740D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
DE60235740T 2001-09-13 2002-09-13 Verfahren und Vorrichtung zur Verzögerungsanpassun Expired - Lifetime DE60235740D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/950,572 US6424190B1 (en) 2001-09-13 2001-09-13 Apparatus and method for delay matching of full and divided clock signals

Publications (1)

Publication Number Publication Date
DE60235740D1 true DE60235740D1 (de) 2010-05-06

Family

ID=25490621

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60235740T Expired - Lifetime DE60235740D1 (de) 2001-09-13 2002-09-13 Verfahren und Vorrichtung zur Verzögerungsanpassun

Country Status (4)

Country Link
US (4) US6424190B1 (de)
EP (1) EP1311066B1 (de)
AT (1) ATE462226T1 (de)
DE (1) DE60235740D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6424190B1 (en) * 2001-09-13 2002-07-23 Broadcom Corporation Apparatus and method for delay matching of full and divided clock signals
US7437633B1 (en) * 2002-09-26 2008-10-14 Xilinx, Inc. Duty cycle characterization and adjustment
US6911856B2 (en) * 2003-07-31 2005-06-28 Qualcomm Inc. Delay matching for clock distribution in a logic circuit
US7489173B1 (en) 2005-02-18 2009-02-10 Xilinx, Inc. Signal adjustment for duty cycle control
US7622965B2 (en) * 2006-01-31 2009-11-24 International Business Machines Corporation Dual-edge shaping latch/synchronizer for re-aligning edges
CN105204600B (zh) * 2015-09-16 2018-10-12 上海斐讯数据通信技术有限公司 一种i2c总线复用实现集成芯片复位方法、***及电子设备
US10840974B1 (en) 2018-04-06 2020-11-17 Rambus Inc. Transmitter/receiver with small-swing level-shifted output

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041738A (en) * 1989-12-04 1991-08-20 Advanced Micro Devices, Inc. CMOS clock generator having an adjustable overlap voltage
JPH04151912A (ja) * 1990-10-16 1992-05-25 Oki Electric Ind Co Ltd 分周回路
US5453707A (en) * 1993-01-13 1995-09-26 Nec Corporation Polyphase clock generation circuit
US5608796A (en) * 1995-02-10 1997-03-04 Lucent Technologies Inc. Balanced phase splitting circuit
US6246278B1 (en) * 1995-12-22 2001-06-12 Lsi Logic Corporation High speed single phase to dual phase clock divider
FR2757330B1 (fr) * 1996-12-18 1999-01-15 Commissariat Energie Atomique Procede de transmission d'informations par reponse impulsionnelle et recepteur correspondant
CA2250538A1 (en) * 1998-10-30 2000-04-30 Mosaid Technologies Incorporated Duty cycle regulator
US6140854A (en) * 1999-01-25 2000-10-31 Motorola, Inc. System with DLL
US6424190B1 (en) * 2001-09-13 2002-07-23 Broadcom Corporation Apparatus and method for delay matching of full and divided clock signals

Also Published As

Publication number Publication date
ATE462226T1 (de) 2010-04-15
EP1311066A3 (de) 2005-02-16
US20050040871A1 (en) 2005-02-24
EP1311066B1 (de) 2010-03-24
US6597216B2 (en) 2003-07-22
US6998885B2 (en) 2006-02-14
US20040017240A1 (en) 2004-01-29
EP1311066A2 (de) 2003-05-14
US6424190B1 (en) 2002-07-23
US6906564B2 (en) 2005-06-14
US20030048119A1 (en) 2003-03-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition