DE60222163D1 - Akkumulations-(mac-)einheit für einzelanweisungs-/ mehrfachdaten-(simd-) anweisungen - Google Patents

Akkumulations-(mac-)einheit für einzelanweisungs-/ mehrfachdaten-(simd-) anweisungen

Info

Publication number
DE60222163D1
DE60222163D1 DE60222163T DE60222163T DE60222163D1 DE 60222163 D1 DE60222163 D1 DE 60222163D1 DE 60222163 T DE60222163 T DE 60222163T DE 60222163 T DE60222163 T DE 60222163T DE 60222163 D1 DE60222163 D1 DE 60222163D1
Authority
DE
Germany
Prior art keywords
mac
unit
simd
data
accumulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60222163T
Other languages
English (en)
Other versions
DE60222163T2 (de
Inventor
Stephen Strazdus
Yuyun Liao
Anthony Jebson
Nigel Paver
Deli Deng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE60222163D1 publication Critical patent/DE60222163D1/de
Application granted granted Critical
Publication of DE60222163T2 publication Critical patent/DE60222163T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Mobile Radio Communication Systems (AREA)
DE60222163T 2001-10-05 2002-10-03 Akkumulations-(mac-)einheit für einzelanweisungs-/ mehrfachdaten-(simd-) anweisungen Expired - Lifetime DE60222163T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/972,720 US7107305B2 (en) 2001-10-05 2001-10-05 Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
US972720 2001-10-05
PCT/US2002/031412 WO2003032187A2 (en) 2001-10-05 2002-10-03 Multiply-accumulate (mac) unit for single-instruction/multiple-data (simd) instructions

Publications (2)

Publication Number Publication Date
DE60222163D1 true DE60222163D1 (de) 2007-10-11
DE60222163T2 DE60222163T2 (de) 2008-06-12

Family

ID=25520040

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60222163T Expired - Lifetime DE60222163T2 (de) 2001-10-05 2002-10-03 Akkumulations-(mac-)einheit für einzelanweisungs-/ mehrfachdaten-(simd-) anweisungen

Country Status (11)

Country Link
US (1) US7107305B2 (de)
EP (1) EP1446728B1 (de)
JP (2) JP4584580B2 (de)
KR (1) KR100834178B1 (de)
CN (1) CN100474235C (de)
AT (1) ATE371893T1 (de)
AU (1) AU2002334792A1 (de)
DE (1) DE60222163T2 (de)
HK (1) HK1065127A1 (de)
TW (1) TWI242742B (de)
WO (1) WO2003032187A2 (de)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6581003B1 (en) * 2001-12-20 2003-06-17 Garmin Ltd. Systems and methods for a navigational device with forced layer switching based on memory constraints
US7532720B2 (en) * 2003-10-15 2009-05-12 Microsoft Corporation Utilizing SIMD instructions within montgomery multiplication
JP4502662B2 (ja) * 2004-02-20 2010-07-14 アルテラ コーポレイション 乗算器−累算器ブロックモード分割
US7353244B2 (en) 2004-04-16 2008-04-01 Marvell International Ltd. Dual-multiply-accumulator operation optimized for even and odd multisample calculations
US20060004903A1 (en) * 2004-06-30 2006-01-05 Itay Admon CSA tree constellation
US8856201B1 (en) 2004-11-10 2014-10-07 Altera Corporation Mixed-mode multiplier using hard and soft logic circuitry
EP1710691A1 (de) * 2005-04-07 2006-10-11 STMicroelectronics (Research & Development) Limited MAC/MUL Einheit
US8620980B1 (en) 2005-09-27 2013-12-31 Altera Corporation Programmable device with specialized multiplier blocks
US8024394B2 (en) 2006-02-06 2011-09-20 Via Technologies, Inc. Dual mode floating point multiply accumulate unit
US8301681B1 (en) 2006-02-09 2012-10-30 Altera Corporation Specialized processing block for programmable logic device
US8266199B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8266198B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8041759B1 (en) * 2006-02-09 2011-10-18 Altera Corporation Specialized processing block for programmable logic device
US7836117B1 (en) 2006-04-07 2010-11-16 Altera Corporation Specialized processing block for programmable logic device
US7822799B1 (en) 2006-06-26 2010-10-26 Altera Corporation Adder-rounder circuitry for specialized processing block in programmable logic device
US7783862B2 (en) * 2006-08-07 2010-08-24 International Characters, Inc. Method and apparatus for an inductive doubling architecture
US8386550B1 (en) 2006-09-20 2013-02-26 Altera Corporation Method for configuring a finite impulse response filter in a programmable logic device
US8122078B2 (en) * 2006-10-06 2012-02-21 Calos Fund, LLC Processor with enhanced combined-arithmetic capability
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US7930336B2 (en) 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US20080140753A1 (en) * 2006-12-08 2008-06-12 Vinodh Gopal Multiplier
US7814137B1 (en) 2007-01-09 2010-10-12 Altera Corporation Combined interpolation and decimation filter for programmable logic device
US8650231B1 (en) 2007-01-22 2014-02-11 Altera Corporation Configuring floating point operations in a programmable device
US7865541B1 (en) 2007-01-22 2011-01-04 Altera Corporation Configuring floating point operations in a programmable logic device
US8645450B1 (en) 2007-03-02 2014-02-04 Altera Corporation Multiplier-accumulator circuitry and methods
US7949699B1 (en) 2007-08-30 2011-05-24 Altera Corporation Implementation of decimation filter in integrated circuit device using ram-based data storage
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8307023B1 (en) 2008-10-10 2012-11-06 Altera Corporation DSP block for implementing large multiplier on a programmable integrated circuit device
US8645449B1 (en) 2009-03-03 2014-02-04 Altera Corporation Combined floating point adder and subtractor
US8706790B1 (en) 2009-03-03 2014-04-22 Altera Corporation Implementing mixed-precision floating-point operations in a programmable integrated circuit device
US8468192B1 (en) 2009-03-03 2013-06-18 Altera Corporation Implementing multipliers in a programmable integrated circuit device
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
JP5376659B2 (ja) * 2009-09-03 2013-12-25 エヌイーシーコンピュータテクノ株式会社 積和演算装置及び積和演算装置の制御方法
US20110055303A1 (en) * 2009-09-03 2011-03-03 Azuray Technologies, Inc. Function Generator
US8396914B1 (en) 2009-09-11 2013-03-12 Altera Corporation Matrix decomposition in an integrated circuit device
US8412756B1 (en) 2009-09-11 2013-04-02 Altera Corporation Multi-operand floating point operations in a programmable integrated circuit device
US8996845B2 (en) * 2009-12-22 2015-03-31 Intel Corporation Vector compare-and-exchange operation
US8539016B1 (en) 2010-02-09 2013-09-17 Altera Corporation QR decomposition in an integrated circuit device
US7948267B1 (en) 2010-02-09 2011-05-24 Altera Corporation Efficient rounding circuits and methods in configurable integrated circuit devices
US8601044B2 (en) 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8484265B1 (en) 2010-03-04 2013-07-09 Altera Corporation Angular range reduction in an integrated circuit device
US8510354B1 (en) 2010-03-12 2013-08-13 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8539014B2 (en) 2010-03-25 2013-09-17 Altera Corporation Solving linear matrices in an integrated circuit device
US8589463B2 (en) 2010-06-25 2013-11-19 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8577951B1 (en) 2010-08-19 2013-11-05 Altera Corporation Matrix operations in an integrated circuit device
US8478969B2 (en) 2010-09-24 2013-07-02 Intel Corporation Performing a multiply-multiply-accumulate instruction
US8645451B2 (en) 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8812576B1 (en) 2011-09-12 2014-08-19 Altera Corporation QR decomposition in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8762443B1 (en) 2011-11-15 2014-06-24 Altera Corporation Matrix operations in an integrated circuit device
US8868634B2 (en) * 2011-12-02 2014-10-21 Advanced Micro Devices, Inc. Method and apparatus for performing multiplication in a processor
CN102520906A (zh) * 2011-12-13 2012-06-27 中国科学院自动化研究所 支持定浮点可重构的向量长度可配置的向量点积累加网络
WO2013095338A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Simd integer multiply-accumulate instruction for multi-precision arithmetic
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9275014B2 (en) * 2013-03-13 2016-03-01 Qualcomm Incorporated Vector processing engines having programmable data path configurations for providing multi-mode radix-2x butterfly vector processing circuits, and related vector processors, systems, and methods
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US10489155B2 (en) 2015-07-21 2019-11-26 Qualcomm Incorporated Mixed-width SIMD operations using even/odd register pairs for wide data elements
CN107977192A (zh) * 2016-10-21 2018-05-01 超威半导体公司 用于执行低功率和低延时多精度计算的方法和***
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
KR102408858B1 (ko) * 2017-12-19 2022-06-14 삼성전자주식회사 비휘발성 메모리 장치, 이를 포함하는 메모리 시스템 및 비휘발성 메모리 장치의 동작 방법
US11409525B2 (en) * 2018-01-24 2022-08-09 Intel Corporation Apparatus and method for vector multiply and accumulate of packed words
WO2020046642A1 (en) 2018-08-31 2020-03-05 Flex Logix Technologies, Inc. Multiplier-accumulator circuit, logic tile architecture for multiply-accumulate and ic including logic tile array
US11194585B2 (en) 2019-03-25 2021-12-07 Flex Logix Technologies, Inc. Multiplier-accumulator circuitry having processing pipelines and methods of operating same
US11314504B2 (en) 2019-04-09 2022-04-26 Flex Logix Technologies, Inc. Multiplier-accumulator processing pipelines and processing component, and methods of operating same
US11288076B2 (en) 2019-09-13 2022-03-29 Flex Logix Technologies, Inc. IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory
US11455368B2 (en) 2019-10-02 2022-09-27 Flex Logix Technologies, Inc. MAC processing pipeline having conversion circuitry, and methods of operating same
US12015428B2 (en) 2019-11-05 2024-06-18 Flex Logix Technologies, Inc. MAC processing pipeline using filter weights having enhanced dynamic range, and methods of operating same
US11693625B2 (en) 2019-12-04 2023-07-04 Flex Logix Technologies, Inc. Logarithmic addition-accumulator circuitry, processing pipeline including same, and methods of operation
US11960856B1 (en) 2020-01-15 2024-04-16 Flex Logix Technologies, Inc. Multiplier-accumulator processing pipeline using filter weights having gaussian floating point data format
US11442881B2 (en) 2020-04-18 2022-09-13 Flex Logix Technologies, Inc. MAC processing pipelines, circuitry to control and configure same, and methods of operating same
US11604645B2 (en) 2020-07-22 2023-03-14 Flex Logix Technologies, Inc. MAC processing pipelines having programmable granularity, and methods of operating same

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3435744B2 (ja) * 1993-09-09 2003-08-11 富士通株式会社 乗算回路
US6385634B1 (en) * 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US5777679A (en) * 1996-03-15 1998-07-07 International Business Machines Corporation Video decoder including polyphase fir horizontal filter
JPH10207863A (ja) * 1997-01-21 1998-08-07 Toshiba Corp 演算処理装置
US5847981A (en) 1997-09-04 1998-12-08 Motorola, Inc. Multiply and accumulate circuit
US6609143B1 (en) * 1998-01-21 2003-08-19 Matsushita Electric Industrial Co., Ltd Method and apparatus for arithmetic operation
JP2000081966A (ja) * 1998-07-09 2000-03-21 Matsushita Electric Ind Co Ltd 演算装置
US6571268B1 (en) * 1998-10-06 2003-05-27 Texas Instruments Incorporated Multiplier accumulator circuits
US6542915B1 (en) * 1999-06-17 2003-04-01 International Business Machines Corporation Floating point pipeline with a leading zeros anticipator circuit
US6532485B1 (en) * 1999-09-08 2003-03-11 Sun Microsystems, Inc. Method and apparatus for performing multiplication/addition operations
US6574651B1 (en) * 1999-10-01 2003-06-03 Hitachi, Ltd. Method and apparatus for arithmetic operation on vectored data
US6611856B1 (en) 1999-12-23 2003-08-26 Intel Corporation Processing multiply-accumulate operations in a single cycle
US6922716B2 (en) * 2001-07-13 2005-07-26 Motorola, Inc. Method and apparatus for vector processing

Also Published As

Publication number Publication date
US20030069913A1 (en) 2003-04-10
US7107305B2 (en) 2006-09-12
DE60222163T2 (de) 2008-06-12
JP2005532601A (ja) 2005-10-27
HK1065127A1 (en) 2005-02-08
ATE371893T1 (de) 2007-09-15
KR100834178B1 (ko) 2008-05-30
EP1446728A2 (de) 2004-08-18
CN1633637A (zh) 2005-06-29
WO2003032187A2 (en) 2003-04-17
EP1446728B1 (de) 2007-08-29
WO2003032187A3 (en) 2004-06-10
AU2002334792A1 (en) 2003-04-22
JP2008217805A (ja) 2008-09-18
JP4584580B2 (ja) 2010-11-24
JP4555356B2 (ja) 2010-09-29
TWI242742B (en) 2005-11-01
KR20040048937A (ko) 2004-06-10
CN100474235C (zh) 2009-04-01

Similar Documents

Publication Publication Date Title
DE60222163D1 (de) Akkumulations-(mac-)einheit für einzelanweisungs-/ mehrfachdaten-(simd-) anweisungen
DE60140899D1 (de) Presspassungs-targetanordnung für hochleistungszerstäubungsvorgang
DE69841492D1 (de) Arithmetischer Prozessor geeignet für verschiedenen endlichen Feldgrösse.
DE60118945D1 (de) Verfahren und vorrichtung für flexible datentypen
AU2003254126A8 (en) Pipelined reconfigurable dynamic instruciton set processor
ATE175039T1 (de) ''pipelined'' verarbeitungseinheit für fliesskommazahlen
BRPI0408645B1 (pt) processo de enrijecimento de um material ao mesmo tempo em que se mantÉm a fluidez do material durante a transferÊncia.
EP1810130A4 (de) Verfahren und vorrichtungen zur zweigvorhersage und verarbeitung von mikroprozessoranweisungen und dergleichen
EP1455271A3 (de) Datenprozessor mit paralleler Decodierung und Ausführung von Daten- und Adressbefehlen
DE69418146T2 (de) Temporärer Registersatz für einen superpipeline-superskalaren Prozessor
IES20080198A2 (en) A processor
DE50114765D1 (de) Schalenkupplung für rohre
DE60313076D1 (de) SIMD Befehle ausführender Prozessor
ATE303717T1 (de) Gutbearbeitungseinheit für einen mähdrescher
ATE413642T1 (de) Benutzung von simd-befehlen innerhalb einer montgomerymultiplizierung
DE60106098D1 (de) Kupplungsanordnung für Abgasrohr
AU2003268043A8 (en) System and method for executing branch instructions in a vliw processor
EP1223505A3 (de) Cachespeicher für arithmetische Rechneroperationen mit teilweisem Übereinstimmen und teilweisem Ausgang
AU2003250361A8 (en) Processor for performing arithmetic operations in composite operands
WO2006075286A3 (en) A processor and its instruction issue method
TW200636493A (en) Unified single-core & multi-mode processor and its program execution method
GB2395298B (en) Flexible results pipeline for processing element
EP1089168A3 (de) Prozessor mit sehr langem Befehlswort
DE60115144D1 (de) Verkettung über unabhängige Zeiger-Prozessoren
EP1220091A3 (de) Schaltungsanordnung und Verfahren zur Befehlskompression und -Verteilung in VLIW-Prozessoren

Legal Events

Date Code Title Description
8364 No opposition during term of opposition