DE602005023597D1 - Verfahren zur Realisierung einer elektrischen Verbindung in einer elektronischen Halbleitervorrichtung zwischen einem nanometrischen Schaltungsarchitektur und elektronischen Standardkomponenten - Google Patents
Verfahren zur Realisierung einer elektrischen Verbindung in einer elektronischen Halbleitervorrichtung zwischen einem nanometrischen Schaltungsarchitektur und elektronischen StandardkomponentenInfo
- Publication number
- DE602005023597D1 DE602005023597D1 DE602005023597T DE602005023597T DE602005023597D1 DE 602005023597 D1 DE602005023597 D1 DE 602005023597D1 DE 602005023597 T DE602005023597 T DE 602005023597T DE 602005023597 T DE602005023597 T DE 602005023597T DE 602005023597 D1 DE602005023597 D1 DE 602005023597D1
- Authority
- DE
- Germany
- Prior art keywords
- realizing
- electrical connection
- electronic device
- circuit architecture
- electronic components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
- B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
- G03F7/70908—Hygiene, e.g. preventing apparatus pollution, mitigating effect of pollution or removing pollutants from apparatus
- G03F7/70916—Pollution mitigation, i.e. mitigating effect of contamination or debris, e.g. foil traps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/81—Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Public Health (AREA)
- Computer Hardware Design (AREA)
- Life Sciences & Earth Sciences (AREA)
- Atmospheric Sciences (AREA)
- Health & Medical Sciences (AREA)
- Epidemiology (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Environmental & Geological Engineering (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05425489A EP1742226B1 (de) | 2005-07-08 | 2005-07-08 | Verfahren zur Realisierung einer elektrischen Verbindung in einer elektronischen Halbleitervorrichtung zwischen einem nanometrischen Schaltungsarchitektur und elektronischen Standardkomponenten |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602005023597D1 true DE602005023597D1 (de) | 2010-10-28 |
Family
ID=35285577
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602005023597T Active DE602005023597D1 (de) | 2005-07-08 | 2005-07-08 | Verfahren zur Realisierung einer elektrischen Verbindung in einer elektronischen Halbleitervorrichtung zwischen einem nanometrischen Schaltungsarchitektur und elektronischen Standardkomponenten |
Country Status (3)
Country | Link |
---|---|
US (2) | US7605066B2 (de) |
EP (1) | EP1742226B1 (de) |
DE (1) | DE602005023597D1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101167176B (zh) * | 2005-02-28 | 2010-06-16 | 意法半导体股份有限公司 | 用于在标准电子元件之间实现纳米电路结构的方法和使用该方法获得的半导体器件 |
EP1741671B1 (de) * | 2005-07-08 | 2010-09-15 | STMicroelectronics Srl | Verfahren zur realisierung einer elektrischen Verbindung in einer elektronischen Halbleitervorrichtung zwischen einem nanometrischen Schaltungsarchitektur und elektronischen Standardkomponenten |
EP1772773B1 (de) * | 2005-10-06 | 2011-06-29 | STMicroelectronics Srl | Methode zur Erzeugung einer mit mehrfachen Linienprofilen umgebenen Struktur, Benutzung einer solchen Struktur als Matrize und Methode zu Herstellung von Schaltkreisstrukturen hiermit |
US8247904B2 (en) * | 2009-08-13 | 2012-08-21 | International Business Machines Corporation | Interconnection between sublithographic-pitched structures and lithographic-pitched structures |
WO2013101230A1 (en) | 2011-12-30 | 2013-07-04 | Intel Corporation | Variable gate width for gate all-around transistors |
CN104951155B (zh) * | 2014-03-31 | 2019-05-17 | 宸盛光电有限公司 | 电容式触控装置及其制作方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4994410A (en) * | 1988-04-04 | 1991-02-19 | Motorola, Inc. | Method for device metallization by forming a contact plug and interconnect using a silicide/nitride process |
JP3216345B2 (ja) * | 1993-04-06 | 2001-10-09 | ソニー株式会社 | 半導体装置及びその作製方法 |
US6268657B1 (en) * | 1995-09-14 | 2001-07-31 | Sanyo Electric Co., Ltd. | Semiconductor devices and an insulating layer with an impurity |
US6403396B1 (en) * | 1998-01-28 | 2002-06-11 | Thin Film Electronics Asa | Method for generation of electrically conducting or semiconducting structures in three dimensions and methods for erasure of the same structures |
US6256767B1 (en) * | 1999-03-29 | 2001-07-03 | Hewlett-Packard Company | Demultiplexer for a molecular wire crossbar network (MWCN DEMUX) |
US6128214A (en) * | 1999-03-29 | 2000-10-03 | Hewlett-Packard | Molecular wire crossbar memory |
US6294450B1 (en) * | 2000-03-01 | 2001-09-25 | Hewlett-Packard Company | Nanoscale patterning for the formation of extensive wires |
US6548881B1 (en) * | 2000-07-25 | 2003-04-15 | Advanced Micro Devices, Inc. | Method and apparatus to achieve bond pad crater sensing and stepping identification in integrated circuit products |
JP2002217195A (ja) * | 2001-01-17 | 2002-08-02 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
DE10308968B4 (de) * | 2003-02-28 | 2006-09-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer leitenden Barrierenschicht mit verbesserter Bedeckung innerhalb kritischer Öffnungen |
US20050052894A1 (en) * | 2003-09-09 | 2005-03-10 | Nantero, Inc. | Uses of nanofabric-based electro-mechanical switches |
US7230286B2 (en) * | 2005-05-23 | 2007-06-12 | International Business Machines Corporation | Vertical FET with nanowire channels and a silicided bottom contact |
US7276424B2 (en) * | 2005-06-29 | 2007-10-02 | Hewlett-Packard Development Company, L.P. | Fabrication of aligned nanowire lattices |
-
2005
- 2005-07-08 DE DE602005023597T patent/DE602005023597D1/de active Active
- 2005-07-08 EP EP05425489A patent/EP1742226B1/de not_active Expired - Fee Related
-
2006
- 2006-07-07 US US11/482,513 patent/US7605066B2/en not_active Expired - Fee Related
-
2009
- 2009-09-28 US US12/568,508 patent/US7928578B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20100019389A1 (en) | 2010-01-28 |
US7605066B2 (en) | 2009-10-20 |
US7928578B2 (en) | 2011-04-19 |
EP1742226B1 (de) | 2010-09-15 |
US20070038966A1 (en) | 2007-02-15 |
EP1742226A1 (de) | 2007-01-10 |
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