DE60125710D1 - Manipulationssichere Methode zur modularen Multiplikation - Google Patents
Manipulationssichere Methode zur modularen MultiplikationInfo
- Publication number
- DE60125710D1 DE60125710D1 DE60125710T DE60125710T DE60125710D1 DE 60125710 D1 DE60125710 D1 DE 60125710D1 DE 60125710 T DE60125710 T DE 60125710T DE 60125710 T DE60125710 T DE 60125710T DE 60125710 D1 DE60125710 D1 DE 60125710D1
- Authority
- DE
- Germany
- Prior art keywords
- tamper
- modular multiplication
- proof method
- proof
- multiplication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/722—Modular multiplication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/728—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using Montgomery reduction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
- G06F2207/7223—Randomisation as countermeasure against side channel attacks
- G06F2207/7257—Random modification not requiring correction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
- G06F7/725—Finite field arithmetic over elliptic curves
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Engineering & Computer Science (AREA)
- Storage Device Security (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001060223 | 2001-03-05 | ||
JP2001060223A JP3950638B2 (ja) | 2001-03-05 | 2001-03-05 | 耐タンパーモジュラ演算処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60125710D1 true DE60125710D1 (de) | 2007-02-15 |
DE60125710T2 DE60125710T2 (de) | 2007-11-08 |
Family
ID=18919673
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60125710T Expired - Lifetime DE60125710T2 (de) | 2001-03-05 | 2001-08-22 | Manipulationssichere Methode zur modularen Multiplikation |
Country Status (4)
Country | Link |
---|---|
US (1) | US6968354B2 (de) |
EP (1) | EP1239364B1 (de) |
JP (1) | JP3950638B2 (de) |
DE (1) | DE60125710T2 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10142155C1 (de) * | 2001-08-29 | 2002-05-23 | Infineon Technologies Ag | Verfahren und Vorrichtung zum modularen Multiplizieren |
JP2003241659A (ja) * | 2002-02-22 | 2003-08-29 | Hitachi Ltd | 情報処理方法 |
US20040001590A1 (en) * | 2002-06-27 | 2004-01-01 | Eisentraeger Anne Kirsten | Efficient elliptic curve double-and-add calculator |
JP4360792B2 (ja) * | 2002-09-30 | 2009-11-11 | 株式会社ルネサステクノロジ | べき乗剰余演算器 |
US7298839B2 (en) | 2003-07-25 | 2007-11-20 | Microsoft Corporation | Squared Weil and Tate pairing techniques for use with elliptic curves |
US7769167B2 (en) | 2003-07-25 | 2010-08-03 | Microsoft Corporation | Weil and Tate pairing techniques using parabolas |
US7440569B2 (en) * | 2003-07-28 | 2008-10-21 | Microsoft Corporation | Tate pairing techniques for use with hyperelliptic curves |
DE10338435B4 (de) * | 2003-08-18 | 2008-12-11 | Infineon Technologies Ag | Schaltung zur Durchführung eines Algorithmus |
JP4713490B2 (ja) * | 2003-11-17 | 2011-06-29 | サンディスク アイエル リミティド | 暗号文メッセージからリトリーブされた平文メッセージの計算をマスクする方法、および、暗号文メッセージをマスクする装置 |
KR100564599B1 (ko) | 2003-12-24 | 2006-03-29 | 삼성전자주식회사 | 역원 계산 회로, 역원계산 방법 및 상기 역원계산 방법을실행시키기 위한 프로그램을 기록한 컴퓨터로 읽을 수있는 기록매체 |
FR2864649B1 (fr) * | 2004-12-23 | 2007-06-01 | Samsung Electronics Co Ltd | Circuit de calcul d'inverse, procede de calcul d'inverse et support d'enregistrement contenant un code de programme lisible par ordinateur |
ATE533103T1 (de) * | 2005-01-18 | 2011-11-15 | Certicom Corp | Beschleunigte verifikation digitaler signaturen und öffentlicher schlüssel |
US7743977B2 (en) * | 2005-02-28 | 2010-06-29 | Broadcom Corporation | Method and system for random data access for security applications |
US8090957B2 (en) | 2005-10-19 | 2012-01-03 | Panasonic Corporation | Information security device, information security method, computer program, computer-readable recording medium, and integrated circuit |
KR100871221B1 (ko) * | 2005-11-11 | 2008-12-01 | 삼성전자주식회사 | 선형 궤환 시프트 레지스터를 이용하는 통신 시스템에서부호 생성 방법 및 장치 |
US20070157030A1 (en) * | 2005-12-30 | 2007-07-05 | Feghali Wajdi K | Cryptographic system component |
KR100808953B1 (ko) | 2006-05-22 | 2008-03-04 | 삼성전자주식회사 | 모듈러곱셈 방법 및 상기 곱셈방법을 수행할 수 있는스마트카드 |
FR2917197B1 (fr) * | 2007-06-07 | 2009-11-06 | Thales Sa | Procede de masquage du resultat d'une operation de multiplication modulaire et dispositif associe. |
EP2015171A1 (de) * | 2007-06-29 | 2009-01-14 | Gemplus | Kryptographieverfahren, das eine gesicherte modulare Potenzierung gegen Angriffe mit verborgenen Kanälen ohne Kenntnis des öffentlichen Exponenten umfasst, Kryptoprozessor zur Umsetzung des Verfahrens und dazugehörige Chipkarte |
US7991162B2 (en) * | 2007-09-14 | 2011-08-02 | University Of Ottawa | Accelerating scalar multiplication on elliptic curve cryptosystems over prime fields |
JP5179933B2 (ja) * | 2008-04-18 | 2013-04-10 | ルネサスエレクトロニクス株式会社 | データ処理装置 |
US8635467B2 (en) | 2011-10-27 | 2014-01-21 | Certicom Corp. | Integrated circuit with logic circuitry and multiple concealing circuits |
US8334705B1 (en) | 2011-10-27 | 2012-12-18 | Certicom Corp. | Analog circuitry to conceal activity of logic circuitry |
US10148285B1 (en) | 2012-07-25 | 2018-12-04 | Erich Schmitt | Abstraction and de-abstraction of a digital data stream |
US9959429B2 (en) * | 2013-03-15 | 2018-05-01 | Cryptography Research, Inc. | Asymmetrically masked multiplication |
US10795858B1 (en) | 2014-02-18 | 2020-10-06 | Erich Schmitt | Universal abstraction and de-abstraction of a digital data stream |
EP3242202A1 (de) * | 2016-05-04 | 2017-11-08 | Gemalto Sa | Gegenmassnahme bei sicheren fehlerangriffen durch fehlerinjektionen auf kryptografischen potenzierungsalgorithmen |
CN108242994B (zh) * | 2016-12-26 | 2021-08-13 | 阿里巴巴集团控股有限公司 | 密钥的处理方法和装置 |
US10601578B2 (en) * | 2017-10-26 | 2020-03-24 | Nxp B.V. | Protecting ECC against fault attacks |
EP3503459B1 (de) * | 2017-12-22 | 2021-04-21 | Secure-IC SAS | Vorrichtung und verfahren zum schutz der ausführung einer kryptographischen operation |
US11522674B1 (en) | 2021-09-09 | 2022-12-06 | Aires Investment Holdings Private Limited | Encryption, decryption, and key generation apparatus and method involving diophantine equation and artificial intelligence |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2726668B1 (fr) * | 1994-11-08 | 1997-01-10 | Sgs Thomson Microelectronics | Procede de mise en oeuvre de reduction modulaire selon la methode de montgomery |
JP3525209B2 (ja) * | 1996-04-05 | 2004-05-10 | 株式会社 沖マイクロデザイン | べき乗剰余演算回路及びべき乗剰余演算システム及びべき乗剰余演算のための演算方法 |
JP3615622B2 (ja) * | 1996-06-28 | 2005-02-02 | 株式会社ルネサステクノロジ | マイクロコンピュータ |
EP0890147B1 (de) * | 1996-10-31 | 2004-02-25 | Atmel Research | Koprozessor zum ausfuehren von modularen multiplikation |
US6748410B1 (en) * | 1997-05-04 | 2004-06-08 | M-Systems Flash Disk Pioneers, Ltd. | Apparatus and method for modular multiplication and exponentiation based on montgomery multiplication |
US6026421A (en) * | 1997-11-26 | 2000-02-15 | Atmel Corporation | Apparatus for multiprecision integer arithmetic |
JP2000165375A (ja) * | 1998-11-30 | 2000-06-16 | Hitachi Ltd | 情報処理装置、icカード |
US6298135B1 (en) * | 1999-04-29 | 2001-10-02 | Motorola, Inc. | Method of preventing power analysis attacks on microelectronic assemblies |
JP3926532B2 (ja) * | 2000-03-16 | 2007-06-06 | 株式会社日立製作所 | 情報処理装置、情報処理方法、及びカード部材 |
US6625631B2 (en) * | 2001-09-28 | 2003-09-23 | Intel Corporation | Component reduction in montgomery multiplier processing element |
-
2001
- 2001-03-05 JP JP2001060223A patent/JP3950638B2/ja not_active Expired - Fee Related
- 2001-08-22 EP EP01119672A patent/EP1239364B1/de not_active Expired - Lifetime
- 2001-08-22 DE DE60125710T patent/DE60125710T2/de not_active Expired - Lifetime
- 2001-08-24 US US09/935,654 patent/US6968354B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20020152252A1 (en) | 2002-10-17 |
EP1239364A1 (de) | 2002-09-11 |
EP1239364B1 (de) | 2007-01-03 |
US6968354B2 (en) | 2005-11-22 |
JP3950638B2 (ja) | 2007-08-01 |
JP2002258743A (ja) | 2002-09-11 |
DE60125710T2 (de) | 2007-11-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8381 | Inventor (new situation) |
Inventor name: KAMINAGA, MASAHIRO, TOKYO, JP Inventor name: ENDO, TAKASHI, TOKYO, JP Inventor name: WATANABE, TAKASHI, TOKYO, JP Inventor name: OHKI, MASARU, TOKYO, JP |
|
8364 | No opposition during term of opposition |