DE60107899D1 - Parallele Datenschnittstelle - Google Patents

Parallele Datenschnittstelle

Info

Publication number
DE60107899D1
DE60107899D1 DE60107899T DE60107899T DE60107899D1 DE 60107899 D1 DE60107899 D1 DE 60107899D1 DE 60107899 T DE60107899 T DE 60107899T DE 60107899 T DE60107899 T DE 60107899T DE 60107899 D1 DE60107899 D1 DE 60107899D1
Authority
DE
Germany
Prior art keywords
data interface
parallel data
interface
parallel
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60107899T
Other languages
English (en)
Other versions
DE60107899T2 (de
Inventor
Andy Pickering
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE60107899D1 publication Critical patent/DE60107899D1/de
Application granted granted Critical
Publication of DE60107899T2 publication Critical patent/DE60107899T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4269—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a handshaking protocol, e.g. Centronics connection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
DE60107899T 2000-05-25 2001-05-25 Parallele Datenschnittstelle Expired - Lifetime DE60107899T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0012813 2000-05-25
GBGB0012813.2A GB0012813D0 (en) 2000-05-25 2000-05-25 Parallel data interface

Publications (2)

Publication Number Publication Date
DE60107899D1 true DE60107899D1 (de) 2005-01-27
DE60107899T2 DE60107899T2 (de) 2006-01-12

Family

ID=9892414

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60107899T Expired - Lifetime DE60107899T2 (de) 2000-05-25 2001-05-25 Parallele Datenschnittstelle

Country Status (4)

Country Link
US (1) US20020006177A1 (de)
EP (1) EP1158415B1 (de)
DE (1) DE60107899T2 (de)
GB (1) GB0012813D0 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552619B2 (en) * 2001-02-05 2003-04-22 Pmc Sierra, Inc. Multi-channel clock recovery circuit
US20030081709A1 (en) * 2001-10-30 2003-05-01 Sun Microsystems, Inc. Single-ended IO with dynamic synchronous deskewing architecture
US7130317B2 (en) * 2001-11-19 2006-10-31 Annadurai Andy P Method and circuit for de-skewing data in a communication system
US7346794B1 (en) * 2005-01-21 2008-03-18 Xilinx, Inc. Method and apparatus for providing clocking phase alignment in a transceiver system
US7688925B2 (en) * 2005-08-01 2010-03-30 Ati Technologies, Inc. Bit-deskewing IO method and system
US8582706B2 (en) * 2009-10-29 2013-11-12 National Instruments Corporation Training a data path for parallel data transfer
US8619931B1 (en) * 2009-11-19 2013-12-31 Altera Corporation Multi-purpose phase-locked loop for low cost transceiver
US8594264B1 (en) * 2010-12-14 2013-11-26 Xilinx, Inc. Phase detection and aligned signal selection with multiple phases of clocks
CN103502965A (zh) * 2011-04-25 2014-01-08 松下电器产业株式会社 信道间时滞调整电路
JP6394130B2 (ja) * 2014-07-09 2018-09-26 株式会社ソシオネクスト 出力回路
US9317639B1 (en) * 2014-10-27 2016-04-19 Freescale Semiconductor, Inc. System for reducing power consumption of integrated circuit
US9935762B2 (en) 2016-07-19 2018-04-03 Qualcomm Incorporated Apparatus and method for centering clock signal in cumulative data eye of parallel data in clock forwarded links

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164677A (en) * 1990-01-16 1992-11-17 Digital Equipment Corporation Method and apparatus for synchronizing signals
DE4025004A1 (de) * 1990-08-07 1992-02-13 Standard Elektrik Lorenz Ag Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signals
US6044121A (en) * 1997-07-22 2000-03-28 Cabletron Systems, Inc. Method and apparatus for recovery of time skewed data on a parallel bus
WO1999046687A1 (fr) * 1998-03-12 1999-09-16 Hitachi, Ltd. Emetteur de donnees
US6700942B1 (en) * 1999-06-30 2004-03-02 Agilent Technologies, Inc. Parallel automatic synchronization system (PASS)
JP2001251283A (ja) * 2000-03-06 2001-09-14 Hitachi Ltd インターフェース回路

Also Published As

Publication number Publication date
EP1158415A3 (de) 2002-07-10
EP1158415B1 (de) 2004-12-22
US20020006177A1 (en) 2002-01-17
GB0012813D0 (en) 2000-07-19
DE60107899T2 (de) 2006-01-12
EP1158415A2 (de) 2001-11-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition