DE60017121D1 - Plattenleitungslesen - Google Patents

Plattenleitungslesen

Info

Publication number
DE60017121D1
DE60017121D1 DE60017121T DE60017121T DE60017121D1 DE 60017121 D1 DE60017121 D1 DE 60017121D1 DE 60017121 T DE60017121 T DE 60017121T DE 60017121 T DE60017121 T DE 60017121T DE 60017121 D1 DE60017121 D1 DE 60017121D1
Authority
DE
Germany
Prior art keywords
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panel line
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Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60017121T
Other languages
English (en)
Other versions
DE60017121T2 (de
Inventor
Johann Alsmeier
Ulrike Gruening
Gerhard Mueller
C O Raist Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE60017121D1 publication Critical patent/DE60017121D1/de
Application granted granted Critical
Publication of DE60017121T2 publication Critical patent/DE60017121T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE60017121T 1999-06-01 2000-05-17 Plattenleitungslesen Expired - Fee Related DE60017121T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US323363 1994-10-14
US09/323,363 US6201730B1 (en) 1999-06-01 1999-06-01 Sensing of memory cell via a plateline
PCT/US2000/013476 WO2000074063A1 (en) 1999-06-01 2000-05-17 Plateline sensing

Publications (2)

Publication Number Publication Date
DE60017121D1 true DE60017121D1 (de) 2005-02-03
DE60017121T2 DE60017121T2 (de) 2006-01-26

Family

ID=23258895

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60017121T Expired - Fee Related DE60017121T2 (de) 1999-06-01 2000-05-17 Plattenleitungslesen

Country Status (8)

Country Link
US (2) US6201730B1 (de)
EP (1) EP1181694B1 (de)
JP (1) JP2003500790A (de)
KR (1) KR100706456B1 (de)
CN (1) CN1227673C (de)
DE (1) DE60017121T2 (de)
TW (1) TW477974B (de)
WO (1) WO2000074063A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383871B1 (en) * 1999-08-31 2002-05-07 Micron Technology, Inc. Method of forming multiple oxide thicknesses for merged memory and logic applications
US6245615B1 (en) * 1999-08-31 2001-06-12 Micron Technology, Inc. Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
JP2002094027A (ja) * 2000-09-11 2002-03-29 Toshiba Corp 半導体記憶装置とその製造方法
US6844583B2 (en) * 2001-06-26 2005-01-18 Samsung Electronics Co., Ltd. Ferroelectric memory devices having expanded plate lines
US6876567B2 (en) * 2001-12-21 2005-04-05 Intel Corporation Ferroelectric memory device and method of reading a ferroelectric memory
GB0229217D0 (en) * 2002-12-14 2003-01-22 Koninkl Philips Electronics Nv Vertical insulated gate transistor and manufacturing method
JP2004335918A (ja) * 2003-05-12 2004-11-25 Toshiba Corp 半導体記憶装置およびその製造方法
KR100618819B1 (ko) * 2004-02-06 2006-08-31 삼성전자주식회사 오버레이 마진이 개선된 반도체 소자 및 그 제조방법
US7262089B2 (en) * 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
US7038231B2 (en) * 2004-04-30 2006-05-02 International Business Machines Corporation Non-planarized, self-aligned, non-volatile phase-change memory array and method of formation
US7316953B2 (en) * 2005-05-31 2008-01-08 Nanya Technology Corporation Method for forming a recessed gate with word lines
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
AU2009273748A1 (en) 2008-07-21 2010-01-28 Sato Holdings Corporation A device having data storage
US8692310B2 (en) 2009-02-09 2014-04-08 Spansion Llc Gate fringing effect based channel formation for semiconductor device
KR20130020333A (ko) 2011-08-19 2013-02-27 삼성전자주식회사 수직형 채널 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
CN104422548B (zh) * 2013-08-28 2016-12-28 中芯国际集成电路制造(北京)有限公司 电容式压力传感器及其形成方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5810864B2 (ja) * 1976-07-05 1983-02-28 株式会社日立製作所 半導体記憶装置
JPS5832789B2 (ja) * 1980-07-18 1983-07-15 富士通株式会社 半導体メモリ
JP2519216B2 (ja) * 1986-08-20 1996-07-31 株式会社東芝 半導体記憶装置
JP2507502B2 (ja) * 1987-12-28 1996-06-12 三菱電機株式会社 半導体装置
US5400275A (en) * 1990-06-08 1995-03-21 Kabushiki Kaisha Toshiba Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected
JP3128262B2 (ja) * 1991-05-28 2001-01-29 株式会社東芝 半導体集積回路装置
JPH05250875A (ja) * 1992-02-27 1993-09-28 Nec Corp 半導体記憶装置
KR960008530B1 (en) * 1992-12-30 1996-06-26 Hyundai Electronics Ind Dram cell
JPH06215564A (ja) * 1993-01-13 1994-08-05 Nec Corp 半導体記憶装置
US5381364A (en) * 1993-06-24 1995-01-10 Ramtron International Corporation Ferroelectric-based RAM sensing scheme including bit-line capacitance isolation
KR950021710A (ko) * 1993-12-01 1995-07-26 김주용 반도체 장치의 캐패시터 제조방법
US5424975A (en) * 1993-12-30 1995-06-13 Micron Technology, Inc. Reference circuit for a non-volatile ferroelectric memory
JP3270294B2 (ja) * 1995-01-05 2002-04-02 株式会社東芝 半導体記憶装置
JP3723599B2 (ja) * 1995-04-07 2005-12-07 株式会社ルネサステクノロジ 半導体記憶装置
DE19519160C1 (de) * 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US5598366A (en) * 1995-08-16 1997-01-28 Ramtron International Corporation Ferroelectric nonvolatile random access memory utilizing self-bootstrapping plate line segment drivers
US5874760A (en) * 1997-01-22 1999-02-23 International Business Machines Corporation 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation
US6337497B1 (en) * 1997-05-16 2002-01-08 International Business Machines Corporation Common source transistor capacitor stack
KR100306823B1 (ko) * 1997-06-02 2001-11-30 윤종용 강유전체메모리셀들을구비한불휘발성메모리장치
US5862089A (en) * 1997-08-14 1999-01-19 Micron Technology, Inc. Method and memory device for dynamic cell plate sensing with ac equilibrate

Also Published As

Publication number Publication date
CN1409860A (zh) 2003-04-09
EP1181694A1 (de) 2002-02-27
EP1181694B1 (de) 2004-12-29
JP2003500790A (ja) 2003-01-07
US6593613B1 (en) 2003-07-15
TW477974B (en) 2002-03-01
WO2000074063A1 (en) 2000-12-07
DE60017121T2 (de) 2006-01-26
CN1227673C (zh) 2005-11-16
KR20020002465A (ko) 2002-01-09
US6201730B1 (en) 2001-03-13
KR100706456B1 (ko) 2007-04-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee