DE60006812D1 - Schaltung zur synchronisation von impulsen, die im jeweils anderen geltungsbereich zweier verschiedener taktsignale erzeugt werden - Google Patents

Schaltung zur synchronisation von impulsen, die im jeweils anderen geltungsbereich zweier verschiedener taktsignale erzeugt werden

Info

Publication number
DE60006812D1
DE60006812D1 DE60006812T DE60006812T DE60006812D1 DE 60006812 D1 DE60006812 D1 DE 60006812D1 DE 60006812 T DE60006812 T DE 60006812T DE 60006812 T DE60006812 T DE 60006812T DE 60006812 D1 DE60006812 D1 DE 60006812D1
Authority
DE
Germany
Prior art keywords
circuit
generated
scope
clock signals
different clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60006812T
Other languages
English (en)
Inventor
Riccardo Gemelli
Marco Pavesi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Italtel SpA
Original Assignee
Italtel SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel SpA filed Critical Italtel SpA
Application granted granted Critical
Publication of DE60006812D1 publication Critical patent/DE60006812D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/102—Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE60006812T 2000-04-17 2000-04-17 Schaltung zur synchronisation von impulsen, die im jeweils anderen geltungsbereich zweier verschiedener taktsignale erzeugt werden Expired - Lifetime DE60006812D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IT2000/000153 WO2001079987A1 (en) 2000-04-17 2000-04-17 Two clock domain pulse to pulse synchronizer

Publications (1)

Publication Number Publication Date
DE60006812D1 true DE60006812D1 (de) 2004-01-08

Family

ID=11133510

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60006812T Expired - Lifetime DE60006812D1 (de) 2000-04-17 2000-04-17 Schaltung zur synchronisation von impulsen, die im jeweils anderen geltungsbereich zweier verschiedener taktsignale erzeugt werden

Country Status (3)

Country Link
EP (1) EP1188108B1 (de)
DE (1) DE60006812D1 (de)
WO (1) WO2001079987A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10255685B3 (de) 2002-11-28 2004-07-29 Infineon Technologies Ag Taktsynchronisationsschaltung
EP1601131B1 (de) 2004-05-24 2007-07-11 STMicroelectronics Limited Asynchrones Mehrfachtaktsystem
US8027420B2 (en) * 2008-03-19 2011-09-27 Itt Manufacturing Enterprises, Inc. Apparatus and method for transferring a signal from a fast clock domain to a slow clock domain

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2537373A1 (fr) * 1982-12-06 1984-06-08 Cit Alcatel Dispositif de traitement de signalisation voie par voie pour autocommutateur temporel
US4873703A (en) * 1985-09-27 1989-10-10 Hewlett-Packard Company Synchronizing system
IT1200896B (it) * 1985-12-18 1989-01-27 Sgs Microelettronica Spa Circuito di risincronizzazione di segnali impulsivi,particolarmente per periferiche di microprocessori
US5905766A (en) * 1996-03-29 1999-05-18 Fore Systems, Inc. Synchronizer, method and system for transferring data
US5987081A (en) * 1997-06-27 1999-11-16 Sun Microsystems, Inc. Method and apparatus for a testable high frequency synchronizer
US6055285A (en) * 1997-11-17 2000-04-25 Qlogic Corporation Synchronization circuit for transferring pointer between two asynchronous circuits
US6260152B1 (en) * 1998-07-30 2001-07-10 Siemens Information And Communication Networks, Inc. Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains

Also Published As

Publication number Publication date
WO2001079987A1 (en) 2001-10-25
EP1188108B1 (de) 2003-11-26
EP1188108A1 (de) 2002-03-20

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