DE59101733D1 - CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR MEMORY BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS. - Google Patents

CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR MEMORY BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS.

Info

Publication number
DE59101733D1
DE59101733D1 DE59101733T DE59101733T DE59101733D1 DE 59101733 D1 DE59101733 D1 DE 59101733D1 DE 59101733 T DE59101733 T DE 59101733T DE 59101733 T DE59101733 T DE 59101733T DE 59101733 D1 DE59101733 D1 DE 59101733D1
Authority
DE
Germany
Prior art keywords
pct
bit patterns
test bit
testing
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE59101733T
Other languages
German (de)
Inventor
Bernhard Dr Lustig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of DE59101733D1 publication Critical patent/DE59101733D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PCT No. PCT/DE91/00685 Sec. 371 Date Mar. 5, 1993 Sec. 102(e) Date Mar. 5, 1993 PCT Filed Aug. 29, 1991 PCT Pub. No. WO92/04717 PCT Pub. Date Mar. 19, 1992.A circuit arrangement for testing a semiconductor memory, in which various test bit patterns can be written into a register (REG) and into memory cell n-tuples (NSPZ), in which the test bit pattern in the register (REG) can be compared with the bit patterns in the memory cell n-tuples (NSPZ) by a multiplicity of comparator circuits (MC), in which the comparator outputs (Mik) are combined by pairs of wired-OR lines to an address matrix (AM), to enable fault location, and in which individual faults (PTSF) and/or multiple faults (PTMF) can be identified by means of a fault type identification circuit (FTE).
DE59101733T 1990-09-11 1991-08-29 CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR MEMORY BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS. Expired - Lifetime DE59101733D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4028819A DE4028819A1 (en) 1990-09-11 1990-09-11 CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR MEMORY BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS
PCT/DE1991/000685 WO1992004717A1 (en) 1990-09-11 1991-08-29 Circuit arrangement for testing a semiconductor store by means of parallel tests with different test bit patterns

Publications (1)

Publication Number Publication Date
DE59101733D1 true DE59101733D1 (en) 1994-06-30

Family

ID=6414039

Family Applications (2)

Application Number Title Priority Date Filing Date
DE4028819A Withdrawn DE4028819A1 (en) 1990-09-11 1990-09-11 CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR MEMORY BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS
DE59101733T Expired - Lifetime DE59101733D1 (en) 1990-09-11 1991-08-29 CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR MEMORY BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS.

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE4028819A Withdrawn DE4028819A1 (en) 1990-09-11 1990-09-11 CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR MEMORY BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS

Country Status (8)

Country Link
US (1) US5436912A (en)
EP (1) EP0548108B1 (en)
JP (1) JP3022990B2 (en)
KR (1) KR100199545B1 (en)
AT (1) ATE106157T1 (en)
DE (2) DE4028819A1 (en)
HK (1) HK59896A (en)
WO (1) WO1992004717A1 (en)

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KR960008824B1 (en) * 1993-11-17 1996-07-05 Samsung Electronics Co Ltd Multi bit test circuit and method of semiconductor memory device
GB9417269D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Memory and test method therefor
JPH0935496A (en) * 1995-07-12 1997-02-07 Advantest Corp Memory tester
US5881250A (en) * 1996-03-15 1999-03-09 Adaptec, Inc. Host adapter system including an integrated PCI buffer controller and XOR function circuit
US5991861A (en) * 1996-03-15 1999-11-23 Adaptec, Inc. Method of enabling and disabling a data function in an integrated circuit
US5867732A (en) * 1996-03-15 1999-02-02 Adaptec, Inc. Hardware method for verifying that an area of memory has only zero values
JP3545535B2 (en) * 1996-05-29 2004-07-21 株式会社アドバンテスト Semiconductor memory test method and apparatus
SE9802800D0 (en) 1998-08-21 1998-08-21 Ericsson Telefon Ab L M Memory supervision
JP3322303B2 (en) * 1998-10-28 2002-09-09 日本電気株式会社 Semiconductor storage device
US6363504B1 (en) * 1999-08-31 2002-03-26 Unisys Corporation Electronic system for testing a set of multiple chips concurrently or sequentially in selectable subsets under program control to limit chip power dissipation
US6363510B1 (en) * 1999-08-31 2002-03-26 Unisys Corporation Electronic system for testing chips having a selectable number of pattern generators that concurrently broadcast different bit streams to selectable sets of chip driver circuits
US6434503B1 (en) 1999-12-30 2002-08-13 Infineon Technologies Richmond, Lp Automated creation of specific test programs from complex test programs
US6421794B1 (en) 2000-03-09 2002-07-16 John T. Chen Method and apparatus for diagnosing memory using self-testing circuits
JP5110771B2 (en) * 2002-12-26 2012-12-26 株式会社半導体エネルギー研究所 Inspection method of semiconductor device
US7574640B2 (en) * 2003-09-05 2009-08-11 Intel Corporation Compacting circuit responses
KR100699827B1 (en) * 2004-03-23 2007-03-27 삼성전자주식회사 Memory module
US8079018B2 (en) * 2007-11-22 2011-12-13 Microsoft Corporation Test impact feedback system for software developers
US8909878B2 (en) 2012-06-12 2014-12-09 International Business Machines Corporation Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3069611D1 (en) * 1979-12-27 1984-12-13 Fujitsu Ltd Apparatus and method for testing semiconductor memory devices
DE3634352A1 (en) * 1986-10-08 1988-04-21 Siemens Ag METHOD AND ARRANGEMENT FOR TESTING MEGA-BIT MEMORY COMPONENTS WITH ANY TEST PATTERN IN MULTI-BIT TEST MODE
JPS63239700A (en) * 1987-03-27 1988-10-05 Ando Electric Co Ltd Data comparing and deciding circuit between ram and rom
GB2222461B (en) * 1988-08-30 1993-05-19 Mitsubishi Electric Corp On chip testing of semiconductor memory devices
JP2780354B2 (en) * 1989-07-04 1998-07-30 富士通株式会社 Semiconductor memory device

Also Published As

Publication number Publication date
HK59896A (en) 1996-04-12
WO1992004717A1 (en) 1992-03-19
DE4028819A1 (en) 1992-03-12
US5436912A (en) 1995-07-25
KR100199545B1 (en) 1999-06-15
EP0548108B1 (en) 1994-05-25
EP0548108A1 (en) 1993-06-30
JPH06500419A (en) 1994-01-13
ATE106157T1 (en) 1994-06-15
KR930702766A (en) 1993-09-09
JP3022990B2 (en) 2000-03-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE