DE4103940A1 - Finely-crystalline soldered joint for joining semiconductor chips to support - using solder foil, temp. of which is held just below the liquids after wetting support - Google Patents

Finely-crystalline soldered joint for joining semiconductor chips to support - using solder foil, temp. of which is held just below the liquids after wetting support

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Publication number
DE4103940A1
DE4103940A1 DE19914103940 DE4103940A DE4103940A1 DE 4103940 A1 DE4103940 A1 DE 4103940A1 DE 19914103940 DE19914103940 DE 19914103940 DE 4103940 A DE4103940 A DE 4103940A DE 4103940 A1 DE4103940 A1 DE 4103940A1
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Germany
Prior art keywords
solder
support
crystalline
solder foil
finely
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19914103940
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German (de)
Inventor
Hans-Juergen Albrecht
Fritz Herbert
Ilona Foest
Brigitte Rathmann
Rainer Rathmann
Wolfgang Scheel
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Humboldt Universitaet zu Berlin
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Humboldt Universitaet zu Berlin
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Priority to DE19914103940 priority Critical patent/DE4103940A1/en
Publication of DE4103940A1 publication Critical patent/DE4103940A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

A process is disclosed for mfg. a mechanically stable, finely crystalline soldered joint, particularly for power electronics components. Amorphous, finely-crystalline or conventional solder materials are used. Soldering is carried out using a solder foil inserted between the metallic or metallised support and the metallised semiconductor chip in an inert gas atmos. The solder foil is applied as a previously-mfd. item to the support. The temp. in the plane of the joint is reduced to 20-30 deg.K below the liquidus of the solder, and held at this level for 10-40 seconds before the application of the metallised chip. After soldering, the complete joint system is cooled to room temp. at 20-28 deg.K/minute. Pref the solder is used in a rapidly-solidified, finely-crystalline form. The rougher side of the solder foil is placed in contact with the support. ADVANTAGE - The wetting of the components by the solder is improved, the chip/solder/support structure has few defects, and the fatigue strength of the joint is improved

Description

Die Erfindung betrifft ein Verfahren zur Herstellung einer thermo-mechanisch stabilen, feinkristallinen Lötverbin­ dung gemäß dem Oberbegriff des Patentanspruches 1, die zur Anwendung in der Leistungselektronik, speziell für die Chipmontage an hochproduktiven Chipbondeinrichtungen, fer­ ner zur löttechnischen Montage eines vereinzelten Halb­ leiterchips auf einem metallischen bzw. metallisierten Trä­ gerelement, insbesondere für Leistungsbauelemente hoher technischer Zuverlässigkeit vorgesehen ist.The invention relates to a method for producing a thermo-mechanically stable, fine crystalline solder joint dung according to the preamble of claim 1, the for use in power electronics, especially for Chip assembly on highly productive chip bonding devices, fer ner for soldering assembly of an isolated half conductor chips on a metallic or metallized carrier gerelement, especially for high power components technical reliability is provided.

Beim Auflöten eines Halbleiterchips auf einem Trägerele­ ment ist es bekannt, das Lot als Lotfolie zwischen Träger­ element und Halbleiterchip zu positionieren.When soldering a semiconductor chip on a carrier element ment it is known to use the solder as a solder foil between the carrier position element and semiconductor chip.

Dieser Prozeßschritt ist fertigungstechnisch einfach. Vor­ handene Oberflächenpassivierungen auf dem Trägerelement, der Rückseitenmetallisierung des Chips sowie dem Lotform­ teil führen jedoch zu dreidimensionalen Benetzungsstörun­ gen in der Fügezone. Die Fügezone sollte aber soweit wie möglich frei von Benetzungsstörungen sein, um hohe Bauele­ mentzuverlässgkeiten zu erreichen. In der DE-PS 36 22 979 A1 wird ein Verfahren zum Befestigen eines Halbleiterchips auf einem metallischen Trägerrahmen beschrieben, welches die Verminderung von nicht zulässigen Hohlräumen und der Nei­ gung zur Verformung und Rißbildung vorsieht. Dazu findet eine vorgeformte Weichlotzwischenlage Anwendung, die eine gleichmäßige Mikrostruktur - frei von Verunreinigungen, wie organische Schichten, sowie intermetallische Verbindungen mit einer Partikelgröße von 10 µm - aufweist. Eine analoge Wirkung wird, unter anderem in der US-PS 44 93 143 sowie in der DE-PS 19 42 880.9-33 beschrieben, unter Verwendung von Lotplättchen erzielt, wobei das Lot mittels Kapillarkräften zwischen Träger und Halbleiterelement verteilt wird. This process step is simple in terms of production technology. Before existing surface passivations on the carrier element, the backside metallization of the chip and the solder form However, some lead to three-dimensional wetting disorders conditions in the joining zone. The joining zone should be as far as possible to be free of wetting disorders to high construction Achieve ment reliability. In DE-PS 36 22 979 A1 discloses a method for mounting a semiconductor chip described a metallic support frame, which the Reduction of inadmissible cavities and nei provides for deformation and cracking. To do this a preformed soft solder liner application that a uniform microstructure - free of impurities, such as organic layers as well as intermetallic compounds with a particle size of 10 microns. An analog one Effect is, inter alia in US-PS 44 93 143 and in the DE-PS 19 42 880.9-33 described using Solder platelet achieved, the solder by means of capillary forces is distributed between the carrier and the semiconductor element.  

In der DE-OS 20 32 939 wird ein weiterer Lösungsvorschlag, eine geometrische Gestaltung des Lotplättchens erörtert. Weitere Verfahrensstabilisierungen sind durch den Ein­ satz von RS-Loten möglich, deren Effektivität und Er­ müdungsstabilität sich durch ein "entsprechend gewähltes" Temperaturregime erhöhen soll, zu dem keine näheren An­ gaben erfolgen.DE-OS 20 32 939 proposes a further solution, discussed a geometrical design of the solder plate. Further procedural stabilizations are through the one set of RS solders possible, their effectiveness and Er fatigue stability through an "appropriately selected" Temperature regime should increase, to which no closer to were given.

Ferner läßt sich in bekannter Weise durch eine optimierte chemische Zusammensetzung der Lote (DE-PS 25 14 922, US-PS 41 70 472), durch hohe Oberflächenreinheit der Lotfolie und der zu lötenden Oberflächen der Rückseitenmetallisie­ rung des Chips und des Trägerelementes, durch die Verwen­ dung von Schutzgas und durch einen strukturierten Träger­ körper (DD-WP 26 54 832) eine verbesserte Fügezone zwischen Chip und Trägerelement zwar erreichen, ob aber dadurch eine für den technischen Anwendungsfall genügende Be­ netzung der Fügeteile über eine Temperaturprofilsteuerung eines Chipbonders ausreichend ist, kann aus den Literatur­ stellen nicht entnommen werden.Furthermore, can be optimized in a known manner chemical composition of the solders (DE-PS 25 14 922, US-PS 41 70 472), due to the high surface purity of the solder foil and the surfaces of the backside metallization to be soldered tion of the chip and the carrier element by the use protection gas and through a structured carrier body (DD-WP 26 54 832) an improved joining zone between Reach the chip and carrier element, but if so a sufficient for the technical application wetting of the parts to be joined via a temperature profile control a chip bonder is sufficient can be found in the literature places are not removed.

In diesem Zusammenhang der ausreichenden thermo-mechani­ schen Stabilität der Fügestelle findet die Problematik zwischen Grenzflächenreaktion und Lotstruktur, die wesent­ lich vom negativen Temperaturgradienten im Lötzyklus ge­ prägt wird, nicht genügend Beachtung bei der Chipmontage.In this context, the sufficient thermomechanical The stability of the joint finds the problem between interface reaction and solder structure, the essential Lich from the negative temperature gradient in the soldering cycle is not sufficiently taken into account when mounting chips.

Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren zur Herstellung einer thermo-mechanisch stabilen, fein­ kristallinen Lötverbindung, insbesondere für Bauelemente der Leistungselektronik zu schaffen, das unter Einsatz schnellerstarrter Lote eine Steigerung der Lotbenetzung auf den Fügeteilen, eine fehlstellenarme Fügezone Chip/ Lot/Trägerelement, eine Verbesserung der Ermüdungsfestig­ keit der Fügezone bei thermodynamischen Belastungen und eine Erhöhung der Stabilität und Zuverlässigkeit der Füge­ zone zwischen Halbleiterchip und Trägerelement ermöglicht. Diese Aufgabe wird durch die im Patentanspruch 1 angege­ benen Maßnahmen gelöst. Eine vorteilhafte Weiterbildung der Erfindung ist im Unteranspruch beschrieben. Erfindungswesentlich ist, daß die durch den Einsatz von schnellerstarrten Loten prädestinierte mikrokristalline Struktur des Lotes und der Fügezone nach Rekristallisa­ tion durch eine gezielte Prozeß- und Temperaturführung weitestgehend erhalten bleibt. Das wird durch eine Zwi­ schenerstarrung nach dem Auflegen der Lotfolie als vor­ gefertigtes Formteil auf das Trägerelement, einen defi­ niert negativen Temperaturgradienten unmittelbar nach dem Chiplöten sowie einer gezielten Positionierung der technologiebedingten rauheren Oberfläche des Lotformtei­ les auf dem Trägerelement erreicht. Darüber hinaus läßt die erfindungsgemäße Prozeßführung zur Herstellung der Lötverbindung eine maximale Lotbenetzung nicht nur in Richtung der Chiprückseite, sondern auch bezüglich des Trägerelementes zu. Die angestrebten Kriterien der Aufga­ benstellung werden insgesamt erreicht und lassen vorteil­ haft eine signifikante Erhöhung der Verfahrens- und technischen Zuverlässigkeit zu.The invention has for its object a method to produce a thermo-mechanically stable, fine crystalline solder connection, especially for components of power electronics to create that using faster solidified solders an increase in solder wetting on the parts to be joined, a low-defect joint zone chip / Solder / support element, an improvement in fatigue strength speed of the joining zone under thermodynamic loads and an increase in the stability and reliability of the joint zone between the semiconductor chip and the carrier element. This object is indicated by the in claim 1 measures resolved. An advantageous further education  the invention is described in the subclaim. It is essential to the invention that through the use of faster solidified solders predestined microcrystalline Structure of the solder and the joining zone according to Rekristallisa tion through targeted process and temperature control largely preserved. That will be through a twos solidification after placing the solder foil as before manufactured molded part on the carrier element, a defi negative temperature gradients immediately after chip soldering and a targeted positioning of the technology-related rougher surface of the solder molding les achieved on the support member. In addition, leaves the process control according to the invention for the production of Solder joint not only in a maximum solder wetting Direction of the back of the chip, but also regarding the Carrier element too. The desired criteria of the task Jobs are achieved overall and leave an advantage a significant increase in procedural and technical reliability too.

Nachfolgend wird die vorliegende Erfindung an Hand eines Ausführungsbeispieles näher erläutert.In the following, the present invention will be explained using a Embodiment explained in more detail.

Zum Einsatz kommen z. B. aus Kupfer oder dessen Kupfer­ legierungen bestehende Trägerelemente, deren Chipmontage­ bereich ganzflächig mit einer Metallisierungsschicht über­ zogen ist, ein schnellerstarrtes Weichlot, z. B. Sn60Pb40, Sn65 Ag25 Sb10, sowie Halbleiterchips mit einer Kanten­ länge bis zu 6 mm. Die Montage erfolgt an hochproduktiven Chipbondern unter Schutzgasatmosphäre nach folgenden Schritten:For example, B. made of copper or its copper alloys existing carrier elements, their chip assembly area over the entire area with a metallization layer is drawn, a quick-set soft solder, z. B. Sn60Pb40, Sn65 Ag25 Sb10, as well as semiconductor chips with one edge length up to 6 mm. The assembly takes place on highly productive Chip bonders in a protective gas atmosphere according to the following Steps:

Schritt 1: LotfolienstationStep 1: solder foil station

Aufbringen eines Lotes in Form eines festen geometrischen Lotformteiles auf das Trägerelement, bei vorzugsweise T=(260 . . . 270)°C. Das Lotformteil wird auf die Träger­ elementoberseite derart aufgelegt, daß die durch die Her­ stellung einer schnellerstarrten Weichlotfolie bedingte Rauhigkeitsdifferenz zwischen den Folienseiten bewußt aus­ genutzt wird. Es wird jene Folienseite der vorgeformten Weichlotzwischenlage auf das metallische Trägerelement auf­ gesetzt, die eine Oberflächenrauhigkeit von (10 . . . 15) µm besitzt. Die dem Chip zugewandte Lotfolienseite weist eine Rauhigkeit im Bereich von (3 . . . 5) µm auf. Durch die erhöhte Oberflächenrauhigkeit ist die benetzungswirksame Oberfläche des Lotes, im Verhältnis zu deren geometrischer Form im Gegensatz zu herkömmlichen Lotfolien wesentlich vergrößert. Gleichzeitig ist dadurch ein Oxidationsschutz der Lotfolie für die nachfolgenden Prozeßschritte gewähr­ leistet, da es an der Lotfolienstation zum sofortigen Auf­ schmelzen und Benetzen zwischen Weichlotfolie und Träger­ element kommt. Die glatte Lotfolienoberseite bietet da­ gegen eine geringere Angriffsfläche gegenüber der Atmosphä­ re.Applying a solder in the form of a solid geometric Solder molded part on the carrier element, preferably T = (260 ... 270) ° C. The solder molding is on the carrier placed on top of the element so that the by Her position of a faster-set soft solder foil Roughness difference between the film sides deliberately  is being used. It becomes the foil side of the preformed one Soft solder liner on the metallic support element which have a surface roughness of (10... 15) µm owns. The solder foil side facing the chip faces a roughness in the range of (3... 5) µm. Through the increased surface roughness is the most effective Surface of the solder, in relation to its geometric Shape in contrast to conventional solder foils enlarged. At the same time, this provides protection against oxidation the solder foil for the subsequent process steps because it opens immediately at the solder foil station melt and wet between soft solder foil and carrier element is coming. The smooth solder foil top offers against a smaller attack surface compared to the atmosphere re.

Schritt 2: ZwischenstationStep 2: intermediate station

Das entsprechend Schritt 1 benetzte Trägerelement wird nach Verlassen der Lotfolienstation, definiert auf eine Tempera­ tur unterhalb des Schmelzpunktes der eingesetzten Lotfolie, auf T=ca. (200 . . . 210)°C abgekühlt und ca. 40 Sekunden auf diesem Niveau gehalten. Durch das erzeugte Temperatur­ gefälle zwischen Schritt 1 und Schritt 2 wird bewußt die feinkristalline homogene Struktur des Lotgefüges erhalten, Voraussetzung für eine hinreichende Qualität der Benetzung, ein gutes Wechsellastverhalten und eine hohe Langzeitstabi­ lität.The carrier element wetted in accordance with step 1 becomes after Leaving the solder foil station, defined to a tempera tur below the melting point of the solder foil used, on T = approx. (200... 210) ° C cooled and about 40 seconds kept at this level. By the temperature generated The difference between step 1 and step 2 is consciously the maintain finely crystalline, homogeneous structure of the solder structure, A prerequisite for adequate wetting quality, good alternating load behavior and high long-term stability lity.

Schritt 3: ChipbondstationStep 3: chip bond station

Im Schritt 3 erfolgt das Löten eines Halbleiterchips auf das, entsprechend Schritt 1 und Schritt 2 vorbereitete Trägerelement, bei einer Temperatur von T=(280 . . . 290)°Cc und einer Andruckkraft des Chips von F = 300 p. Bei der obengenannten Temperatur liegt das Lot im schmelzflüssigen Zustand vor. Die Zeit oberhalb der Liquidustemperatur des Lotwerkstoffes ist identisch mit der Mindestzeit, die für den Lötprozeß, kausal bestimmt durch die Kinetik des Be­ netzungsvorganges zwischen Lotformteil/Halbleiterchip, benötigt wird und beträgt t=(4 . . . 7) s. In step 3, a semiconductor chip is soldered on that prepared according to step 1 and step 2 Carrier element, at a temperature of T = (280 ... 290) ° Cc and a pressing force of the chip of F = 300 p. In the The above-mentioned temperature is in the molten liquid Condition before. The time above the liquidus temperature of the Solder material is identical to the minimum time required for the soldering process, causally determined by the kinetics of the loading wetting process between molded solder part / semiconductor chip, is required and is t = (4... 7) s.  

Schritt 4: AusfahrstationStep 4: exit station

Hierbei wird das gesamte Fügesystem innerhalb kürzester Zeit - t = 10 s - von Löttemperatur (siehe Schritt 3) auf Raumtemperatur abgekühlt. Durch diese "Abschreckung" wird das Rekristallisationsverhalten derart gesteuert, daß das durch die Schnellerstarrung ursprünglich erzielte fein­ kristalline Lotgefüge auch nach der technologischen Ver­ arbeitung der Lotfolie erhalten bzw. wiederhergestellt wird.The entire joining system is within a very short time Time - t = 10 s - from soldering temperature (see step 3) Cooled to room temperature. This "deterrence" will the recrystallization behavior controlled so that the originally achieved by the rapid solidification fine crystalline solder structure even after the technological ver Work on the solder foil received or restored becomes.

Claims (2)

1. Verfahren zur Herstellung einer thermo-mechanisch sta­ bilen, feinkristallinen Lötverbindung, insbesondere für Bauelemente der Leistungselektronik, wobei unter Ver­ wendung amorpher oder feinkristalliner oder konventio­ neller Lotwerkstoffe das Lot als Lotfolie zwischen me­ tallischen oder metallisiertem Trägerelement und metalli­ siertem Halbleiterchip unter Schutzgasatmosphäre gelötet wird, dadurch gekennzeichnet, daß nach dem Aufbringen der Lotfolie als vorgefertigtes Formteil auf das Träger­ element und vor dem eigentlichen Lötprozeß des rücksei­ ten-metallisierten Halbleiterchips/Lotfolie/Träger­ elements in der Verbindungsebene, das Temperaturniveau nach der Lotfolienaufnahme und Aufschmelzung um DT = (20-30) K unter dem Liquiduspunkt des Lotes abgesenkt und bei t = 10 bis 40 Sekunden gehalten wird und anschließend nach dem Lötprozeß das gesamte Füge­ system mit einer genau definierten Abkühlungsgeschwindig­ keit von -DT/Dt = (20-28) K 1 auf Raumtem­ peratur gebracht wird.1. A method for producing a thermo-mechanically stable, finely crystalline solder connection, in particular for components in power electronics, the solder being soldered as a solder foil between metallic or metallized carrier element and metallized semiconductor chip under an inert gas atmosphere using amorphous or finely crystalline or conventional solder materials , characterized in that after the application of the solder foil as a prefabricated molded part to the carrier element and before the actual soldering process of the rear-side metallized semiconductor chip / solder foil / carrier element in the connection plane, the temperature level after the solder foil pickup and melting by DT = (20- 30) K is lowered below the liquidus point of the solder and is held at t = 10 to 40 seconds and then after the soldering process the entire joining system with a precisely defined cooling speed of -DT / Dt = (20-28) K 1 at room temperature brought . 2. Verfahren zur Herstellung nach Anspruch 1, dadurch ge­ kennzeichnet, daß bei Verwendung von schnellerstarrten, feinst- oder feinkristallinen Lotformteilen die Positio­ nierung der Lotfolie vorzugsweise mit der rauheren Ober­ flächenseite auf das Trägerelement vorgenommen wird.2. A method for producing according to claim 1, characterized ge indicates that when using rigid, ultra-fine or fine-crystalline solder molded parts the position Nation of the solder foil preferably with the rougher upper Flat side is made on the carrier element.
DE19914103940 1991-02-07 1991-02-07 Finely-crystalline soldered joint for joining semiconductor chips to support - using solder foil, temp. of which is held just below the liquids after wetting support Withdrawn DE4103940A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19914103940 DE4103940A1 (en) 1991-02-07 1991-02-07 Finely-crystalline soldered joint for joining semiconductor chips to support - using solder foil, temp. of which is held just below the liquids after wetting support

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19914103940 DE4103940A1 (en) 1991-02-07 1991-02-07 Finely-crystalline soldered joint for joining semiconductor chips to support - using solder foil, temp. of which is held just below the liquids after wetting support

Publications (1)

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DE4103940A1 true DE4103940A1 (en) 1992-08-13

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DE19914103940 Withdrawn DE4103940A1 (en) 1991-02-07 1991-02-07 Finely-crystalline soldered joint for joining semiconductor chips to support - using solder foil, temp. of which is held just below the liquids after wetting support

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