DE3880825T2 - Anordnung zur schnellen addition von binärzahlen. - Google Patents

Anordnung zur schnellen addition von binärzahlen.

Info

Publication number
DE3880825T2
DE3880825T2 DE88907975T DE3880825T DE3880825T2 DE 3880825 T2 DE3880825 T2 DE 3880825T2 DE 88907975 T DE88907975 T DE 88907975T DE 3880825 T DE3880825 T DE 3880825T DE 3880825 T2 DE3880825 T2 DE 3880825T2
Authority
DE
Germany
Prior art keywords
arrangement
binary numbers
fast addition
fast
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88907975T
Other languages
English (en)
Other versions
DE3880825D1 (de
Inventor
Edwin Kelley
Howard Baller
Randall Conilogue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of DE3880825D1 publication Critical patent/DE3880825D1/de
Application granted granted Critical
Publication of DE3880825T2 publication Critical patent/DE3880825T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Analogue/Digital Conversion (AREA)
DE88907975T 1987-08-25 1988-08-18 Anordnung zur schnellen addition von binärzahlen. Expired - Fee Related DE3880825T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8918187A 1987-08-25 1987-08-25

Publications (2)

Publication Number Publication Date
DE3880825D1 DE3880825D1 (de) 1993-06-09
DE3880825T2 true DE3880825T2 (de) 1993-11-11

Family

ID=22216157

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88907975T Expired - Fee Related DE3880825T2 (de) 1987-08-25 1988-08-18 Anordnung zur schnellen addition von binärzahlen.

Country Status (5)

Country Link
US (1) US5132921A (de)
EP (1) EP0344226B1 (de)
JP (1) JPH02501242A (de)
DE (1) DE3880825T2 (de)
WO (1) WO1989002120A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5347482A (en) * 1992-12-14 1994-09-13 Hal Computer Systems, Inc. Multiplier tree using nine-to-three adders
US5406506A (en) * 1993-11-09 1995-04-11 United Microelectronics Corp. Domino adder circuit having MOS transistors in the carry evaluating paths
US5491653A (en) * 1994-10-06 1996-02-13 International Business Machines Corporation Differential carry-save adder and multiplier
US6037891A (en) * 1998-02-23 2000-03-14 Motorola, Inc. Low power serial analog-to-digital converter
DE69909924T2 (de) * 1998-09-09 2004-03-11 Texas Instruments Inc., Dallas Verfahren und Vorrichtung zur Reduzierung der Verlustleistung in einer Schaltung
FR2789192B1 (fr) * 1999-02-02 2001-04-20 Thomson Csf Additionneur chainable rapide a retenue anticipee
US6625634B1 (en) * 1999-10-01 2003-09-23 Sun Microsystems, Inc. Efficient implementation of multiprecision arithmetic

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3519810A (en) * 1967-02-14 1970-07-07 Motorola Inc Logic element (full adder) using transistor tree-like configuration
US3535502A (en) * 1967-11-15 1970-10-20 Ibm Multiple input binary adder
DE2007353C3 (de) * 1970-02-18 1973-11-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Vierteiliges Addierwerk
US4052604A (en) * 1976-01-19 1977-10-04 Hewlett-Packard Company Binary adder
US4215418A (en) * 1978-06-30 1980-07-29 Trw Inc. Integrated digital multiplier circuit using current mode logic
US4228520A (en) * 1979-05-04 1980-10-14 International Business Machines Corporation High speed multiplier using carry-save/propagate pipeline with sparse carries
US4449197A (en) * 1982-03-10 1984-05-15 Bell Telephone Laboratories, Incorporated One-bit full adder circuit
DE3323607A1 (de) * 1983-06-30 1985-01-03 Siemens AG, 1000 Berlin und 8000 München Digitales rechenwerk
US4677584A (en) * 1983-11-30 1987-06-30 Texas Instruments Incorporated Data processing system with an arithmetic logic unit having improved carry look ahead
JPS60205631A (ja) * 1984-03-29 1985-10-17 Toshiba Corp 全加算回路
SU1191906A1 (ru) * 1984-04-29 1985-11-15 Московский Ордена Трудового Красного Знамени Инженерно-Физический Институт Сумматор по модулю два
US4689763A (en) * 1985-01-04 1987-08-25 Advanced Micro Devices, Inc. CMOS full adder circuit
WO1986004699A1 (en) * 1985-01-31 1986-08-14 Burroughs Corporation Fast bcd/binary adder
DE3524797A1 (de) * 1985-07-11 1987-01-22 Siemens Ag Anordnung zur bitparallelen addition von binaerzahlen
BR8602717A (pt) * 1985-09-11 1987-04-14 Sperry Corp Aparelho para efetuar adicao de binarios

Also Published As

Publication number Publication date
JPH02501242A (ja) 1990-04-26
US5132921A (en) 1992-07-21
DE3880825D1 (de) 1993-06-09
EP0344226B1 (de) 1993-05-05
WO1989002120A1 (en) 1989-03-09
EP0344226A1 (de) 1989-12-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee