DE3855860D1 - Schaltungsveränderungssystem und -verfahren, Verfahren zur Erzeugung von invertierter Logik und Logikentwurfssystem - Google Patents

Schaltungsveränderungssystem und -verfahren, Verfahren zur Erzeugung von invertierter Logik und Logikentwurfssystem

Info

Publication number
DE3855860D1
DE3855860D1 DE3855860T DE3855860T DE3855860D1 DE 3855860 D1 DE3855860 D1 DE 3855860D1 DE 3855860 T DE3855860 T DE 3855860T DE 3855860 T DE3855860 T DE 3855860T DE 3855860 D1 DE3855860 D1 DE 3855860D1
Authority
DE
Germany
Prior art keywords
logic
circuit change
generating inverted
design system
change system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855860T
Other languages
English (en)
Other versions
DE3855860T2 (de
Inventor
Tamotsu Nishiyama
Noriko Matsumoto
Masahiko Ueda
Masahiko Matsunaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62241288A external-priority patent/JPS6482263A/ja
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE3855860D1 publication Critical patent/DE3855860D1/de
Publication of DE3855860T2 publication Critical patent/DE3855860T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S706/00—Data processing: artificial intelligence
    • Y10S706/902—Application using ai with detail of the ai system
    • Y10S706/919—Designing, planning, programming, CAD, CASE
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S706/00—Data processing: artificial intelligence
    • Y10S706/902—Application using ai with detail of the ai system
    • Y10S706/919—Designing, planning, programming, CAD, CASE
    • Y10S706/921—Layout, e.g. circuit, construction

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Devices For Executing Special Programs (AREA)
  • Image Processing (AREA)
DE3855860T 1987-09-25 1988-09-26 Schaltungsveränderungssystem und -verfahren, Verfahren zur Erzeugung von invertierter Logik und Logikentwurfssystem Expired - Fee Related DE3855860T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62241288A JPS6482263A (en) 1987-09-25 1987-09-25 Circuit conversion system
JP1294188 1988-01-22
JP6108288 1988-03-15

Publications (2)

Publication Number Publication Date
DE3855860D1 true DE3855860D1 (de) 1997-05-15
DE3855860T2 DE3855860T2 (de) 1997-10-16

Family

ID=27280054

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855860T Expired - Fee Related DE3855860T2 (de) 1987-09-25 1988-09-26 Schaltungsveränderungssystem und -verfahren, Verfahren zur Erzeugung von invertierter Logik und Logikentwurfssystem

Country Status (4)

Country Link
US (1) US5043914A (de)
EP (1) EP0309292B1 (de)
JP (1) JP2506991B2 (de)
DE (1) DE3855860T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5095441A (en) * 1986-09-12 1992-03-10 Digital Equipment Corporation Rule inference and localization during synthesis of logic circuit designs
JPH02259836A (ja) * 1989-03-31 1990-10-22 Hitachi Ltd フアジイ推論方法
JPH03116237A (ja) * 1989-09-29 1991-05-17 Hitachi Ltd 知識処理方法
JP3049561B2 (ja) * 1990-05-21 2000-06-05 東洋通信機株式会社 プロダクションシステムとプロダクションシステムの変換装置
GB2246883B (en) * 1990-08-07 1995-01-11 Matsushita Electric Ind Co Ltd Inference processor
JPH05274390A (ja) * 1992-03-30 1993-10-22 Matsushita Electric Ind Co Ltd 回路素子割り付け方法及び遅延最適化方法並びに論理設計システム
JP2840169B2 (ja) * 1992-12-28 1998-12-24 松下電器産業株式会社 論理回路の自動設計方法およびその装置
US5903470A (en) * 1993-02-17 1999-05-11 Matsushita Electric Industrial Co., Ltd. Method and apparatus for automatically designing logic circuit, and multiplier
JP2972498B2 (ja) * 1993-09-02 1999-11-08 松下電器産業株式会社 論理回路の自動設計方法、そのシステム及びその装置並びに乗算器
US5648911A (en) * 1993-12-21 1997-07-15 Grodstein; Joel Joseph Method of minimizing area for fanout chains in high-speed networks
US5734798A (en) * 1995-12-01 1998-03-31 Hewlett-Packard Co. Method and apparatus for extracting a gate modeled circuit from a fet modeled circuit
US5808896A (en) * 1996-06-10 1998-09-15 Micron Technology, Inc. Method and system for creating a netlist allowing current measurement through a sub-circuit
US6701289B1 (en) * 1997-01-27 2004-03-02 Unisys Corporation Method and apparatus for using a placement tool to manipulate cell substitution lists
US6009249A (en) * 1997-06-13 1999-12-28 Micron Technology, Inc. Automated load determination for partitioned simulation
US7136888B2 (en) 2000-08-04 2006-11-14 Arithmatica Limited Parallel counter and a logic circuit for performing multiplication
GB2365636B (en) 2000-08-04 2005-01-05 Automatic Parallel Designs Ltd A parallel counter and a multiplication logic circuit
US6883011B2 (en) 2000-08-04 2005-04-19 Arithmatica Limited Parallel counter and a multiplication logic circuit
JP2004506260A (ja) * 2000-08-04 2004-02-26 オートマティック・パラレル・デザインズ・リミテッド 並列計数器と乗算を実行するための論理回路
GB2373602B (en) 2001-03-22 2004-11-17 Automatic Parallel Designs Ltd A multiplication logic circuit
US20030005786A1 (en) * 2001-07-05 2003-01-09 Microdexterity Systems, Inc. Parallel mechanism
US6971083B1 (en) 2002-11-13 2005-11-29 Altera Corporation Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
US7260595B2 (en) 2002-12-23 2007-08-21 Arithmatica Limited Logic circuit and method for carry and sum generation and method of designing such a logic circuit
US6909767B2 (en) 2003-01-14 2005-06-21 Arithmatica Limited Logic circuit
US7042246B2 (en) 2003-02-11 2006-05-09 Arithmatica Limited Logic circuits for performing threshold functions
US7308471B2 (en) 2003-03-28 2007-12-11 Arithmatica Limited Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding
GB2401962B (en) 2003-05-23 2005-05-18 Arithmatica Ltd A sum bit generation circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703435A (en) * 1984-07-16 1987-10-27 International Business Machines Corporation Logic Synthesizer
JPS6274158A (ja) * 1985-09-27 1987-04-04 Hitachi Ltd 回路変換方式
JPS62194578A (ja) * 1985-10-21 1987-08-27 Hitachi Ltd 論理回路の製造方式

Also Published As

Publication number Publication date
DE3855860T2 (de) 1997-10-16
JPH01315874A (ja) 1989-12-20
EP0309292A2 (de) 1989-03-29
EP0309292A3 (de) 1991-05-02
JP2506991B2 (ja) 1996-06-12
US5043914A (en) 1991-08-27
EP0309292B1 (de) 1997-04-09

Similar Documents

Publication Publication Date Title
DE3855860D1 (de) Schaltungsveränderungssystem und -verfahren, Verfahren zur Erzeugung von invertierter Logik und Logikentwurfssystem
DE3778962D1 (de) Vorrichtung zur erzeugung von kuenstlichen wirbelwinden.
DE3789650D1 (de) Verfahren und System zur Festkörpermodellierung.
DE3852413D1 (de) Verfahren und System zur Erzeugung von visuellen Bildern.
DE3880547D1 (de) System und verfahren zum kodieren von gegenstaenden.
DE3585743D1 (de) Verfahren zur erzeugung von bildern.
DE69019179D1 (de) Verfahren und Gerät zur Erzeugung von mehrfarbigen Bildern.
DE69005652D1 (de) Gerät und Verfahren zur Erzeugung von Spurregelsignalen.
DE3870633D1 (de) Verfahren zur herstellung von butyrolactonen und von butandiolen.
DE68905688D1 (de) Verfahren zur erzeugung von zusammengesetzten metallteilen.
DE3680482D1 (de) Verfahren zur herstellung von sulfomethylpolyacrylamid-polymeren und sulfomethyl-einheiten enthaltende polymere.
DE68917125D1 (de) Verfahren zur Erzeugung von graphischen Modellen und rechnergestütztes Entwurfssystem.
DE3873094D1 (de) Verfahren zur aufbereitung von gas.
DE3689356D1 (de) Verfahren und Schaltung zum Generieren von binären Signalen und modifizierter Bitfolge.
DE3670552D1 (de) Anlage und verfahren zur erzeugung von digitalbildern.
DE3881685D1 (de) Kombiniertes verfahren zur erzeugung von chlordioxid und natriumhydroxid.
DE3769024D1 (de) Verfahren und vorrichtung zur uebertragung von artikeln.
DE3683556D1 (de) Verfahren zur generierung von alkali.
DE3684511D1 (de) Verfahren zur herstellung von l-threonin und l-isoleucin.
DE3684922D1 (de) Verfahren zur herstellung von 2-phenylbenzotriazolen und 2-phenylbenzotriazol-n-oxyden.
DE3853253D1 (de) Verfahren und System zur Sequenzsteuerung.
DE3870558D1 (de) Verfahren zur erzeugung und verteilung von geheimschluesseln.
DE3789645D1 (de) Verfahren und System zur Erzeugung von Objekttransformationsbildern.
DE3578601D1 (de) Verfahren und schaltungsanordnung zur erzeugung von farbhintergrundsignalen.
DE69029974D1 (de) Gerät und Verfahren zur Erzeugung von Signalen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee