DE3850224D1 - Verbindungstechnik mit dielektrischen Schichten. - Google Patents
Verbindungstechnik mit dielektrischen Schichten.Info
- Publication number
- DE3850224D1 DE3850224D1 DE3850224T DE3850224T DE3850224D1 DE 3850224 D1 DE3850224 D1 DE 3850224D1 DE 3850224 T DE3850224 T DE 3850224T DE 3850224 T DE3850224 T DE 3850224T DE 3850224 D1 DE3850224 D1 DE 3850224D1
- Authority
- DE
- Germany
- Prior art keywords
- dielectric layers
- connection technology
- technology
- connection
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
- H01L2224/49176—Wire connectors having the same loop shape and height
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85203—Thermocompression bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
- Y10T156/1092—All laminae planar and face to face
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
- Y10T156/1092—All laminae planar and face to face
- Y10T156/1093—All laminae planar and face to face with covering of discrete laminae with additional lamina
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Combinations Of Printed Boards (AREA)
- Manufacturing Of Electrical Connectors (AREA)
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/125,975 US4843191A (en) | 1987-11-27 | 1987-11-27 | Interconnection technique using dielectric layers |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3850224D1 true DE3850224D1 (de) | 1994-07-21 |
DE3850224T2 DE3850224T2 (de) | 1994-09-22 |
Family
ID=22422354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3850224T Expired - Fee Related DE3850224T2 (de) | 1987-11-27 | 1988-11-18 | Verbindungstechnik mit dielektrischen Schichten. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4843191A (de) |
EP (1) | EP0318209B1 (de) |
JP (1) | JPH01167970A (de) |
DE (1) | DE3850224T2 (de) |
HK (1) | HK127595A (de) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4981817A (en) * | 1988-12-29 | 1991-01-01 | International Business Machines Corporation | Tab method for implementing dynamic chip burn-in |
US5067004A (en) * | 1989-12-13 | 1991-11-19 | Digital Equipment Corporation | Module for interconnecting integrated circuits |
JP2749422B2 (ja) * | 1990-02-20 | 1998-05-13 | キヤノン株式会社 | 記録電極 |
US5155302A (en) * | 1991-06-24 | 1992-10-13 | At&T Bell Laboratories | Electronic device interconnection techniques |
US5225633A (en) * | 1991-10-04 | 1993-07-06 | The United States Of America As Represented By The Secretary Of The Air Force | Bridge chip interconnect system |
US5604330A (en) * | 1994-12-29 | 1997-02-18 | Intel Corporation | Staggered land pad pattern on substrate for tab interconnection |
US6603079B2 (en) * | 1999-02-05 | 2003-08-05 | Mack Technologies Florida, Inc. | Printed circuit board electrical interconnects |
US6507495B1 (en) * | 2000-06-28 | 2003-01-14 | Dell Products L.P. | Three-dimensional technique for improving the EMC characteristics of a printed circuit board |
JP2005340385A (ja) * | 2004-05-25 | 2005-12-08 | Nitto Denko Corp | 配線回路基板および配線回路基板の接続構造 |
US8860635B2 (en) * | 2005-04-04 | 2014-10-14 | The Invention Science Fund I, Llc | Self assembling display with substrate |
US8334819B2 (en) * | 2005-03-11 | 2012-12-18 | The Invention Science Fund I, Llc | Superimposed displays |
US7662008B2 (en) * | 2005-04-04 | 2010-02-16 | Searete Llc | Method of assembling displays on substrates |
US20060202944A1 (en) * | 2005-03-11 | 2006-09-14 | Searete Llc, A Limited Liability Corporation Of The State Of Delaware | Elements for self assembling displays |
US7990349B2 (en) * | 2005-04-22 | 2011-08-02 | The Invention Science Fund I, Llc | Superimposed displays |
US8711063B2 (en) * | 2005-03-11 | 2014-04-29 | The Invention Science Fund I, Llc | Self assembly of elements for displays |
US7977130B2 (en) | 2006-08-03 | 2011-07-12 | The Invention Science Fund I, Llc | Method of assembling displays on substrates |
US8300007B2 (en) * | 2005-03-11 | 2012-10-30 | The Invention Science Fund I, Llc | Self assembling display with substrate |
US9153163B2 (en) * | 2005-03-11 | 2015-10-06 | The Invention Science Fund I, Llc | Self assembly of elements for displays |
US8390537B2 (en) * | 2005-03-11 | 2013-03-05 | The Invention Science Fund I, Llc | Method of assembling displays on substrates |
US7834466B2 (en) * | 2007-12-17 | 2010-11-16 | Freescale Semiconductor, Inc. | Semiconductor die with die pad pattern |
CN105307392B (zh) * | 2015-10-16 | 2018-10-19 | 武汉华星光电技术有限公司 | 一种印刷电路板及电子设备 |
TWI708539B (zh) * | 2019-04-10 | 2020-10-21 | 欣興電子股份有限公司 | 印刷電路板堆疊結構及其形成方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54153360U (de) * | 1978-04-18 | 1979-10-25 | ||
US4255613A (en) * | 1979-06-15 | 1981-03-10 | Rockwell International Corporation | Electrical interconnect |
JPS5717734U (de) * | 1980-07-03 | 1982-01-29 | ||
US4472762A (en) * | 1980-09-25 | 1984-09-18 | Texas Instruments Incorporated | Electronic circuit interconnection system |
US4546406A (en) * | 1980-09-25 | 1985-10-08 | Texas Instruments Incorporated | Electronic circuit interconnection system |
US4385202A (en) * | 1980-09-25 | 1983-05-24 | Texas Instruments Incorporated | Electronic circuit interconnection system |
EP0120500B1 (de) * | 1983-03-29 | 1989-08-16 | Nec Corporation | LSI Verpackung hoher Dichte für logische Schaltungen |
US4674808A (en) * | 1985-11-12 | 1987-06-23 | Fairchild Semiconductor Corporation | Signal ground planes for tape bonded devices |
US4811082A (en) * | 1986-11-12 | 1989-03-07 | International Business Machines Corporation | High performance integrated circuit packaging structure |
-
1987
- 1987-11-27 US US07/125,975 patent/US4843191A/en not_active Expired - Lifetime
-
1988
- 1988-11-18 DE DE3850224T patent/DE3850224T2/de not_active Expired - Fee Related
- 1988-11-18 EP EP88310884A patent/EP0318209B1/de not_active Expired - Lifetime
- 1988-11-24 JP JP63294870A patent/JPH01167970A/ja active Granted
-
1995
- 1995-08-10 HK HK127595A patent/HK127595A/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US4843191A (en) | 1989-06-27 |
EP0318209A2 (de) | 1989-05-31 |
JPH01167970A (ja) | 1989-07-03 |
EP0318209A3 (en) | 1990-06-13 |
DE3850224T2 (de) | 1994-09-22 |
JPH0530038B2 (de) | 1993-05-07 |
EP0318209B1 (de) | 1994-06-15 |
HK127595A (en) | 1995-08-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN |
|
8339 | Ceased/non-payment of the annual fee |