DE3788485D1 - Verfahren zur Herstellung einer Planarleiterbahn durch isotropes Abscheiden von leitendem Werkstoff. - Google Patents
Verfahren zur Herstellung einer Planarleiterbahn durch isotropes Abscheiden von leitendem Werkstoff.Info
- Publication number
- DE3788485D1 DE3788485D1 DE87201755T DE3788485T DE3788485D1 DE 3788485 D1 DE3788485 D1 DE 3788485D1 DE 87201755 T DE87201755 T DE 87201755T DE 3788485 T DE3788485 T DE 3788485T DE 3788485 D1 DE3788485 D1 DE 3788485D1
- Authority
- DE
- Germany
- Prior art keywords
- openings
- insulating layer
- planar
- production
- conductive material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000008021 deposition Effects 0.000 title abstract 2
- 239000004020 conductor Substances 0.000 title 2
- 239000000463 material Substances 0.000 abstract 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract 1
- 229910052721 tungsten Inorganic materials 0.000 abstract 1
- 239000010937 tungsten Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Multi-Conductor Connections (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US91342886A | 1986-09-30 | 1986-09-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3788485D1 true DE3788485D1 (de) | 1994-01-27 |
DE3788485T2 DE3788485T2 (de) | 1994-06-09 |
Family
ID=25433265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3788485T Expired - Lifetime DE3788485T2 (de) | 1986-09-30 | 1987-09-14 | Verfahren zur Herstellung einer Planarleiterbahn durch isotropes Abscheiden von leitendem Werkstoff. |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0262719B1 (de) |
JP (1) | JP2573621B2 (de) |
KR (1) | KR960009091B1 (de) |
AT (1) | ATE98814T1 (de) |
CA (1) | CA1294716C (de) |
DE (1) | DE3788485T2 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0682660B2 (ja) * | 1987-08-17 | 1994-10-19 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | 導電性スタツドを形成する方法 |
US4847111A (en) * | 1988-06-30 | 1989-07-11 | Hughes Aircraft Company | Plasma-nitridated self-aligned tungsten system for VLSI interconnections |
KR910006744B1 (ko) * | 1988-07-21 | 1991-09-02 | 삼성전자 주식회사 | 접속창 채움방법 |
GB2233494A (en) * | 1989-06-26 | 1991-01-09 | Philips Nv | Providing an electrode on a semiconductor device |
EP0430040A3 (en) * | 1989-11-27 | 1992-05-20 | Micron Technology, Inc. | Method of forming a conductive via plug or an interconnect line of ductile metal within an integrated circuit using mechanical smearing |
US5244534A (en) * | 1992-01-24 | 1993-09-14 | Micron Technology, Inc. | Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs |
KR950010854B1 (ko) * | 1992-10-30 | 1995-09-25 | 현대전자산업주식회사 | 텅스텐 플러그 형성방법 |
EP0971409A1 (de) * | 1998-07-07 | 2000-01-12 | Interuniversitair Micro-Elektronica Centrum Vzw | Herstellungsverfahren von Kupfer enthaltenden Metallstützen |
EP0971403A1 (de) | 1998-07-07 | 2000-01-12 | Interuniversitair Microelektronica Centrum Vzw | Herstellungsverfahren von Kupfer enthaltenden Metallstützen |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1286737A (en) * | 1969-10-15 | 1972-08-23 | Itt | Multilevel conductive systems |
JPS61112353A (ja) * | 1984-11-07 | 1986-05-30 | Nec Corp | 多層配線の形成方法 |
US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
GB2186424A (en) * | 1986-01-30 | 1987-08-12 | Plessey Co Plc | Method for producing integrated circuit interconnects |
EP0234407A1 (de) * | 1986-02-28 | 1987-09-02 | General Electric Company | Verfahren zum Auffüllen von Verbindungs- oder Kontaktlöchern in einer mehrlagigen VLSI-Metallisierungsstruktur |
-
1987
- 1987-09-14 DE DE3788485T patent/DE3788485T2/de not_active Expired - Lifetime
- 1987-09-14 EP EP87201755A patent/EP0262719B1/de not_active Expired - Lifetime
- 1987-09-14 AT AT87201755T patent/ATE98814T1/de not_active IP Right Cessation
- 1987-09-24 CA CA000547692A patent/CA1294716C/en not_active Expired - Lifetime
- 1987-09-25 JP JP62240595A patent/JP2573621B2/ja not_active Expired - Lifetime
- 1987-09-28 KR KR1019870010770A patent/KR960009091B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960009091B1 (ko) | 1996-07-10 |
EP0262719A2 (de) | 1988-04-06 |
DE3788485T2 (de) | 1994-06-09 |
EP0262719B1 (de) | 1993-12-15 |
ATE98814T1 (de) | 1994-01-15 |
CA1294716C (en) | 1992-01-21 |
JPS6390838A (ja) | 1988-04-21 |
EP0262719A3 (en) | 1988-12-14 |
KR880004609A (ko) | 1988-06-07 |
JP2573621B2 (ja) | 1997-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0335459A3 (de) | Elektrische Leitungen für elektronische Bauelemente | |
EP0343667A3 (de) | Kontaktstruktur um eine Elektrode an einem Halbleiterbauelement zu verbinden und ihr Herstellungsverfahren | |
KR960702172A (ko) | 수직 접속된 반도체 부품을 형성하기 위한 방법(process for producing vertically connected semiconductor components) | |
TW351848B (en) | A method of integrating a porous dielectric layer into a semiconductor device and a semiconductor device thus fabricated | |
ATE229231T1 (de) | Verfahren zur herstellung einer halbleiteranordnung mit einer leitfähigen schicht | |
DE3788485D1 (de) | Verfahren zur Herstellung einer Planarleiterbahn durch isotropes Abscheiden von leitendem Werkstoff. | |
DE3485704D1 (de) | Verfahren zur herstellung von leitfaehigen, durchgehenden loechern durch eine dielektrische schicht. | |
EP0323856A3 (de) | Substratsstruktur für zusammengesetztes Halbleiterbauelement | |
US4487993A (en) | High density electronic circuits having very narrow conductors | |
DE3482546D1 (de) | Plasmaverfahren zur herstellung leitfaehiger durchgehender loecher durch eine dielektrische schicht. | |
US3586922A (en) | Multiple-layer metal structure and processing | |
ATE86797T1 (de) | Verfahren zur selbstjustierten herstellung von kontakten zwischen in uebereinander angeordneten verdrahtungsebenen einer integrierten schaltung enthaltenen leiterbahnen. | |
EP0358350A3 (de) | Ausbilden eines vorgeschriebenen Musters auf einer Schicht eines Halbleiterelements | |
DE2902665C2 (de) | ||
DE3578618D1 (de) | Verfahren zur herstellung von halbleiteranordnungen mit einer ueberlagerten schicht aus polykristallinem silizium. | |
EP0394722A3 (de) | Mehrlagen-Metallverbindungen für VLSI und Verfahren zum Herstellen derselben | |
KR890011035A (ko) | 집적회로 제조방법 및 전기접속 형성방법 | |
KR900002407A (ko) | 반도체 소자 제조방법 | |
EP0818946A3 (de) | Gedruckte Leiterplatte und Verfahren zu deren Herstellung | |
JPS6448423A (en) | Dividing method of semiconductor chip | |
JPS6486508A (en) | Manufacture of chip capacitor | |
WO1995028000A3 (en) | Method of manufacturing a semiconductor device with a multilayer wiring structure containing narrow vias | |
EP0346625A3 (de) | Verfahren zur Herstellung eines integrierten Halbleiterschaltkreises mit Isolationsgräben | |
EP0206481A3 (de) | Halbleiteranordnung mit Mehrschichtbedrahtung | |
JPS6484735A (en) | Manufacture of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N |
|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NXP B.V., EINDHOVEN, NL |