DE3575226D1 - Anordnung und verfahren zur herstellung eines eprom. - Google Patents
Anordnung und verfahren zur herstellung eines eprom.Info
- Publication number
- DE3575226D1 DE3575226D1 DE8585305914T DE3575226T DE3575226D1 DE 3575226 D1 DE3575226 D1 DE 3575226D1 DE 8585305914 T DE8585305914 T DE 8585305914T DE 3575226 T DE3575226 T DE 3575226T DE 3575226 D1 DE3575226 D1 DE 3575226D1
- Authority
- DE
- Germany
- Prior art keywords
- eprom
- producing
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/18—Circuits for erasing optically
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59171451A JPS6150351A (ja) | 1984-08-20 | 1984-08-20 | Eprom装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3575226D1 true DE3575226D1 (de) | 1990-02-08 |
Family
ID=15923343
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585305914T Expired - Fee Related DE3575226D1 (de) | 1984-08-20 | 1985-08-20 | Anordnung und verfahren zur herstellung eines eprom. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4723156A (de) |
EP (1) | EP0175489B1 (de) |
JP (1) | JPS6150351A (de) |
KR (1) | KR900007229B1 (de) |
DE (1) | DE3575226D1 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6150353A (ja) * | 1984-08-20 | 1986-03-12 | Oki Electric Ind Co Ltd | Eprom装置 |
US4890152A (en) * | 1986-02-14 | 1989-12-26 | Matsushita Electric Works, Ltd. | Plastic molded chip carrier package and method of fabricating the same |
EP0268181B1 (de) * | 1986-11-15 | 1992-07-29 | Matsushita Electric Works, Ltd. | Gegossenes Kunststoff-Chip-Gehäuse mit Steckermuster |
US4939569A (en) * | 1989-02-27 | 1990-07-03 | Corning Incorporated | Ultraviolet transmitting glasses for EPROM windows |
US5834799A (en) * | 1989-08-28 | 1998-11-10 | Lsi Logic | Optically transmissive preformed planar structures |
FR2667982B1 (fr) * | 1990-10-15 | 1997-07-25 | Sgs Thomson Microelectronics | Boitier moule de circuit integre a fenetre et procede de moulage. |
US5196919A (en) * | 1990-12-07 | 1993-03-23 | Kyocera America, Inc. | Use of a contamination shield during the manufacture of semiconductor packages |
US5598034A (en) * | 1992-07-22 | 1997-01-28 | Vlsi Packaging Corporation | Plastic packaging of microelectronic circuit devices |
US5406699A (en) * | 1992-09-18 | 1995-04-18 | Matsushita Electric Industrial Co., Ltd. | Method of manufacturing an electronics package |
US5324888A (en) * | 1992-10-13 | 1994-06-28 | Olin Corporation | Metal electronic package with reduced seal width |
US5355016A (en) * | 1993-05-03 | 1994-10-11 | Motorola, Inc. | Shielded EPROM package |
US5436407A (en) * | 1994-06-13 | 1995-07-25 | Integrated Packaging Assembly Corporation | Metal semiconductor package with an external plastic seal |
US5410181A (en) * | 1994-06-20 | 1995-04-25 | Motorola, Inc. | Assembly for mounting an electronic device having an optically erasable surface |
US5770889A (en) * | 1995-12-29 | 1998-06-23 | Lsi Logic Corporation | Systems having advanced pre-formed planar structures |
JPH1197656A (ja) * | 1997-09-22 | 1999-04-09 | Fuji Electric Co Ltd | 半導体光センサデバイス |
DE19958229B4 (de) * | 1998-12-09 | 2007-05-31 | Fuji Electric Co., Ltd., Kawasaki | Optisches Halbleiter-Sensorbauelement |
JP2004119863A (ja) * | 2002-09-27 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置およびその製造方法 |
US7902644B2 (en) * | 2007-12-07 | 2011-03-08 | Stats Chippac Ltd. | Integrated circuit package system for electromagnetic isolation |
US9099391B2 (en) * | 2013-03-14 | 2015-08-04 | Infineon Technologies Austria Ag | Semiconductor package with top-side insulation layer |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6015152B2 (ja) * | 1980-01-09 | 1985-04-17 | 株式会社日立製作所 | 樹脂封止半導体メモリ装置 |
JPS56137660A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device |
JPS5759364A (en) * | 1980-09-29 | 1982-04-09 | Hitachi Ltd | Semiconductor device |
JPS5895844A (ja) * | 1981-12-01 | 1983-06-07 | Toshiba Corp | 半導体装置 |
JPS58106851A (ja) * | 1981-12-18 | 1983-06-25 | Nec Corp | 半導体装置 |
JPS58140250A (ja) * | 1982-02-16 | 1983-08-19 | 東レ株式会社 | 成形用複合フイルム |
JPS58207656A (ja) * | 1982-05-28 | 1983-12-03 | Fujitsu Ltd | 樹脂封止型半導体装置およびその製造方法 |
JPS60117696A (ja) * | 1983-11-30 | 1985-06-25 | 沖電気工業株式会社 | Epromの実装構造 |
-
1984
- 1984-08-20 JP JP59171451A patent/JPS6150351A/ja active Pending
-
1985
- 1985-08-05 KR KR1019850005637A patent/KR900007229B1/ko not_active IP Right Cessation
- 1985-08-20 EP EP85305914A patent/EP0175489B1/de not_active Expired - Lifetime
- 1985-08-20 DE DE8585305914T patent/DE3575226D1/de not_active Expired - Fee Related
-
1987
- 1987-07-06 US US07/070,123 patent/US4723156A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4723156A (en) | 1988-02-02 |
JPS6150351A (ja) | 1986-03-12 |
EP0175489B1 (de) | 1990-01-03 |
KR860002142A (ko) | 1986-03-26 |
EP0175489A3 (en) | 1987-08-19 |
KR900007229B1 (ko) | 1990-10-05 |
EP0175489A2 (de) | 1986-03-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |