DE3023410A1 - Miniaturisation method for MOS structures - employs trench etching and deposit of silicon compound - Google Patents

Miniaturisation method for MOS structures - employs trench etching and deposit of silicon compound

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Publication number
DE3023410A1
DE3023410A1 DE19803023410 DE3023410A DE3023410A1 DE 3023410 A1 DE3023410 A1 DE 3023410A1 DE 19803023410 DE19803023410 DE 19803023410 DE 3023410 A DE3023410 A DE 3023410A DE 3023410 A1 DE3023410 A1 DE 3023410A1
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source
gate
drain
trench etching
drain regions
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DE19803023410
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Egon Dipl.-Phys. Dr. 8000 München Bußmann
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

In order to increase miniturization in the fabrication of MOS structures the method makes tolerances less critical by automatic alignment of gate and source-drain regions and increasing the conductivity of source, drain and gate. This is achieved by separating the source-drain diffusion from the field diffusion by means of trench etching and depositing of silicon compound on source-drain regions. Gate-oxide is deposited on a substrate and the subsequent implantation employs conventional photolacquer masking. A further step comprises the structuring of source-drain regions with trench etching and p-implantation. This is followed by filling with silicon oxide whose selective growth results in self- alignment of gate and contact regions.

Description

Verfahren zur Herstellung von MOS-Strukturen.Process for the production of MOS structures.

Die Erfindung betrifft ein Verfahren zur Herstellung von MOS-Strukturen nach dem LOCOS-Verfahren mit kleinen Abmessungen bei niedriger Temperatur. Unter niedriger Temperatur ist ein Tmperaturbereich von 5500 bis 800°C zu verstehen.The invention relates to a method for producing MOS structures according to the LOCOS process with small dimensions at low temperature. Under a temperature range of 5500 to 800 ° C is to be understood.

Es hat sich gezeigt, daß man mit dem Isoplanarverfahren - auch LOCOS-Verfahren (local oxidation of silicon) genannt - in Verbindung mit einer besonderen Technologie zum Anbringen von B-dotierten Bereichen eine drastische Reduktion der erforderlichen Oberfläche erzielen kann.It has been shown that the isoplanar method - also LOCOS method (local oxidation of silicon) - in connection with a special technology for attaching B-doped areas a drastic reduction in the required Surface can achieve.

In der LOCOS-Technologie wird der Gatebereich mit einer Siliziumnitridschicht auf Siliziumdioxid und Silizium während des Feldoxidaufbaus abgedeckt. Nach Abätzen dieser Schichtkombination wird das Gateoxid besonders aufgebaut.In LOCOS technology, the gate area is covered with a silicon nitride layer covered on silicon dioxide and silicon during field oxide build-up. After etching The gate oxide is specially built up with this layer combination.

Auch auf diesem Spezialgebiet wird eine weitergehende Miniaturisierung angestrebt. Der Erfindung liegt die Aufgabe zugrunde, die Justier-Toleranz für die Erzeugung kleiner Strukturen durch die Selbstjustierung des Gates sowie der Source-Drain Bereiche zwischen den Feldoxiden und der Source-Drain-Kontakte unkritischer zu machen und ferner die Leitfähigkeit von Source, Drain und Gate zu erhöhen.Further miniaturization is also taking place in this special field strived for. The invention is based on the object of the adjustment tolerance for Creation of small structures through the self-alignment of the gate and the source-drain To make areas between the field oxides and the source-drain contacts less critical and further increase the conductivity of the source, drain and gate.

Diese Aufgabe wird gemäß der Erfindung dadurch erreicht, daß eine Trennung der Source-Drain-Dotierung von der Felddotierung durch eine Grabenätzung erfolgt. Auf diese T;.rei se wird erreicht, daß durch das unterschiedliche T;chstum die Selbstjustierung des Gates sowie der Source- und Drainbereiche zwischen den Feldoxiden und der Source-Drain-Kontakte unkritischer gemacht wird. Das bedeutet praktisch eine Vorustierung des Gatebereiches.This object is achieved according to the invention in that a Separation of the source-drain doping from the field doping by trench etching he follows. On this journey it is achieved that through the different cultures the Self-alignment of the gate and the source and drain areas between the field oxides and the source-drain contacts are made less critical. That means practically pre-testing of the gate area.

Zur Steigerung dieses effekts wird nach einer Teiterbildung der Erfindung Silizid über den Source-Drain-Gebieten abgeschieden. Dabei wird zusätzlich eine Leitfähigkeitserhöhung erreicht.To increase this effect, the invention is further developed Silicide deposited over the source-drain regions. An Increase in conductivity achieved.

Nach einer Weiterbildung der Erfindung wird eine Durchoxidation der Polyschicht zur endgültigen gleichzeitigen Definition der Gate- und Kontaktgebiete vorgenommen. Dadurch erfolgt eine gleichzeitige festlegung des Gates und der Source-Drain-Kontakte. Die Erfindung wird anhand der Figuren an zwei Ausführungsbeispielen erläutert. Es zeigen: Figur 1 eine Ausführung A in einer Variante I, Figur 2 parallel dazu eine Variante II und Figur 3 eine Ausführung B.According to a further development of the invention, through oxidation of the Poly layer for the final simultaneous definition of the gate and contact areas performed. This results in a simultaneous definition of the gate and the source-drain contacts. The invention is explained with reference to the figures using two exemplary embodiments. It show: FIG. 1 an embodiment A in a variant I, FIG. 2 a parallel thereto Variant II and Figure 3 an embodiment B.

Bei den Varianten I und II sind die einzelnen Verfahrensschritte immer nebeneinander angeordnet, tun die Unterschiede besonders hersuszustellen. Gleichbleibende Schritte sind nur einmal dargestellt. Beim ersten Verfahrensschritt nach der Ausführung A, der auch für die Ausführung B gilt, handelt es sich um das Erzeugen des Gateoxid mit Kanalimplantation, z. B. B+. Auf einem Substrat 1 ist ein Gateoxid aufgebracht, das in der Figur mit 2 gekennzeichnet ist. Mit den Pfeilen ist die Implantationsrichtung angedeutet.With variants I and II, the individual process steps are always the same Arranged next to each other, the differences are particularly evident. Consistent Steps are only shown once. At the first step after execution A, which also applies to version B, is the generation of the gate oxide with canal implantation, e.g. B. B +. A gate oxide is applied to a substrate 1, which is marked with 2 in the figure. The direction of implantation is indicated by the arrows indicated.

Der nächste Vorgang, das Strukturieren des Gateoxidbereiches sowie die n+-Implantation wird ausland der Variante II erläutert. Bei der Variante I ist dieser Vorgang nicht vorhanden. Bei diesem Schritt II erfolgen die Source-Drain-Dotierungen. Auf das Gateoxid 2 wird eine Fotolackstruktur (Fötotechnik 1) als Maske für die n+-Implantation aufgebracht.The next process, the structuring of the gate oxide area as well the n + implantation will be carried out abroad Variant II explained. at variant I does not have this process. Take place at this step II the source-drain doping. A photoresist structure (photo technique 1) applied as a mask for the n + implantation.

Beim Schritt 3, der ebenfalls nur bei der Variante II vorkommt, wird Wolfram oder 1:Tolframsilizid ganzflächig mit Ausnahme des Gateoxidbereichs abgeschieden. Mit n+ sind die im vorhergehenden Schritt aufgebrachten Implantationen gekennzeichnet.In step 3, which also only occurs in variant II, Tungsten or 1: tolfram silicide deposited over the entire area with the exception of the gate oxide area. The implants applied in the previous step are marked with n +.

Der Schritt 4 umfaßt das Strukturieren der Source-Drain-Bereiche, Grabenätzen und p+-Feldimp'lantation. Zu-dieser Stufe gehört die Fototechnik 2. Aus beiden Varianten I und II ist die Trennung der Source-Drain-Gebiete ersichtlich. Unter der G?'abenä'tzung L ist jeweils eine p-Implantation 5 angedeutet. Die vorher aufgebrachte Fotolackstruktur ist mit 6 bezeichnet. In der Variante II werden durch die Grabenätzung die Source-Drain-Gebiete getrennt.Step 4 comprises structuring the source-drain regions, Trench etching and p + field implantation. Photo technology 2 belongs to this stage. The separation of the source-drain regions can be seen from both variants I and II. A p-implantation 5 is indicated in each case under the etching L. The one before The applied photoresist structure is denoted by 6. In variant II, the trench etching separates the source-drain regions.

Der Schritt 5, der für beide Varianten gilt, aber-nur bei der Variante I dargestellt ist, umfaßt das Änfüllen der Gräben mit Siliziumoxid. Das abgeschiedene Siliziumoxid ist mit 7 gekennzeichnet.Step 5, which applies to both variants, but only for the variant I includes filling the trenches with silicon oxide. The secluded Silicon oxide is marked 7.

Der Verfahrensschritt 6 gilt nur für die Variante I. Dabei wird auf die im Schritt 2 in Variante II entsprechende Form die Lackstruktur 3 aufgebracht und die Söurce-Drain-Gebiete durch Implantation n+ definiert. Dabei dient das in der Ätzgrube abgeschiedene Siliziumoxid als Ionenfänger.Process step 6 only applies to variant I. This is based on the form corresponding to step 2 in variant II, the lacquer structure 3 is applied and the soil drain regions are defined by implantation n +. The in the etching pit deposited silicon oxide as an ion trap.

Der Verfahrens schritt 7 gilt für beide Varianten, obwohl er nur in der Variante I dargestellt ist. Dabei erfolgt eine ganzflächige Polysiliziumabscheidung.Procedure step 7 applies to both variants, although it is only in variant I is shown. A polysilicon deposition occurs over the entire area.

Nach Schritt 8 der Variante I wird sowohl über den Source-Drain-Kontakten als auch über den Gate eine Fotolaclrnitridstruktur 9 bzw. eine Fotolacknitridsilizidstruktur 10 (Fototechnik 3) definiert. Wenn in diesem Schritt die Polydotierung ausgeführt wird, so vereinfacht dies die Selbstjustierung des Gates.After step 8 of variant I, both the source-drain contacts as well as a photoresist nitride structure 9 or a photoresist nitride silicide structure via the gate 10 (photo technique 3). When doing the poly doping in this step this simplifies the self-adjustment of the gate.

Im Schritt 9 der Varianten I und II werden durch die Durchoxidation des Polysiliziums Gateelektrode und Source-Drain-Kontakte definiert. 11 bezeichnet das dementsprechende Oxid. Da Siliziumoxid bei tiefen Temperaturen über n+-dotierten Gebieten sowie über Siliziden stärker wächst als lateral über das Gateoxid ergibt sich eine Selbstjustierung des Gate.In step 9 of the variants I and II are through the oxidation of the polysilicon gate electrode and source-drain contacts are defined. 11 designated the corresponding oxide. Since silicon oxide doped more than n + at low temperatures Areas as well as over silicides grows stronger than laterally over the gate oxide results self-adjustment of the gate.

Nach der Ausführung B in der Figur 3 ist wiederum ein Substrat 1 mit einer Lackmaske 3 versehen. Im Schritt 1 erfolgt die Source-Drain-Implantation n+.According to embodiment B in FIG. 3, a substrate 1 is again included a lacquer mask 3 is provided. In step 1, the source-drain implantation n + takes place.

Im Schritt 2 ist die Trennung der Source-Drain-Gebiete durch Grabenätzung dargestellt. In diesem Schritt erfolgt gleichzeitig eine p+-Implantation.In step 2, the source-drain regions are separated by trench etching shown. In this step, a p + implantation takes place at the same time.

Im Schritt 3 wird ganzflächig das Gateoxid 2 aufgebracht, wobei das unterschiedliche Oxidwachstum über den n+-Gebieten ausgenützt wird.In step 3, the gate oxide 2 is applied over the entire area, the different oxide growth over the n + regions is exploited.

Der Schritt 4 in Ausführung B entspricht Schritt 7 in Ausführung A und der Schritt 5 der Ausführung B dem Verfahrensschritt 8 der Ausführung A. Der Endzustand in der Ausführung B ist mit dem Verfahrensschritt 9 der Ausführung A gleich.Step 4 in execution B corresponds to step 7 in execution A. and step 5 of execution B to method step 8 of execution A. The The final state in execution B is with method step 9 of execution A same.

Analog zu Variation 2 der Ausführung A ist auch hierbei eine Variation II mit Siliziden möglich.Analogous to variation 2 of version A, there is also a variation here II possible with silicides.

3 Patentansprtlche 3 Figuren3 patent claims 3 figures

Claims (3)

PatentansPrüche .Patent claims. 1. Verfahren zur Herstellung von MOS-Strukturen nach dem LOCOS-Verfahren mit kleinen Abmessungen bei niedriger Temperatur, d a du r c h g e k e n n z e i c h n e t daß eine Trennung der Source-Drain-Dotierung von der Feiddotierung durch eine Grabenätzung erfolgt.1. Process for the production of MOS structures according to the LOCOS process with small dimensions at low temperature, d u r c h e k e n n z e i c h n e t that the source-drain doping is separated from the field doping a trench etching takes place. 2. Verfahren nach Anspruch 1, d a d u r c h g e -k e n n z e i c h n e t , daß Silizide über den Source-Drain-Gebieten abgeschieden werden.2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that silicides are deposited over the source-drain regions. 3. Verfahren nach den Ansprüchen 1 und 2, d a d u r c h g e k e n n z e i c h n e t , daß eine Durchoxidation der Polyschicht zur gleichzeitigen endgültigen Definition der Gate- und Kontaktgebiete vorgenommen wird.3. The method according to claims 1 and 2, d a d u r c h g e k e n It should be noted that through oxidation of the poly layer for simultaneous final Definition of the gate and contact areas is made.
DE19803023410 1980-06-23 1980-06-23 Miniaturisation method for MOS structures - employs trench etching and deposit of silicon compound Ceased DE3023410A1 (en)

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EP0074541A2 (en) * 1981-09-10 1983-03-23 Fujitsu Limited Method for the production of a semiconductor device comprising dielectrically isolating regions
EP0113517A2 (en) * 1982-11-29 1984-07-18 Fujitsu Limited Method for forming an isolation region
EP0236123A2 (en) * 1986-03-04 1987-09-09 Seiko Epson Corporation A semiconductor device and method for preparing the same

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074541A2 (en) * 1981-09-10 1983-03-23 Fujitsu Limited Method for the production of a semiconductor device comprising dielectrically isolating regions
EP0074541A3 (en) * 1981-09-10 1984-06-06 Fujitsu Limited Method for the production of a semiconductor device comprising dielectrically isolating regions
US4506434A (en) * 1981-09-10 1985-03-26 Fujitsu Limited Method for production of semiconductor devices
EP0113517A2 (en) * 1982-11-29 1984-07-18 Fujitsu Limited Method for forming an isolation region
EP0113517A3 (en) * 1982-11-29 1986-06-11 Fujitsu Limited Method for forming an isolation region
EP0236123A2 (en) * 1986-03-04 1987-09-09 Seiko Epson Corporation A semiconductor device and method for preparing the same
EP0236123A3 (en) * 1986-03-04 1988-07-20 Seiko Epson Corporation A semiconductor device and method for preparing the same

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