DE2967321D1 - High density memory system - Google Patents
High density memory systemInfo
- Publication number
- DE2967321D1 DE2967321D1 DE7979901181T DE2967321T DE2967321D1 DE 2967321 D1 DE2967321 D1 DE 2967321D1 DE 7979901181 T DE7979901181 T DE 7979901181T DE 2967321 T DE2967321 T DE 2967321T DE 2967321 D1 DE2967321 D1 DE 2967321D1
- Authority
- DE
- Germany
- Prior art keywords
- high density
- memory system
- density memory
- memory
- density
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/939,297 US4183095A (en) | 1978-09-01 | 1978-09-01 | High density memory device |
PCT/US1979/000675 WO1980000632A1 (en) | 1978-09-01 | 1979-08-28 | High density memory system |
Publications (1)
Publication Number | Publication Date |
---|---|
DE2967321D1 true DE2967321D1 (en) | 1985-01-17 |
Family
ID=25472902
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE7979901181T Expired DE2967321D1 (en) | 1978-09-01 | 1979-08-28 | High density memory system |
Country Status (5)
Country | Link |
---|---|
US (1) | US4183095A (de) |
EP (1) | EP0016827B1 (de) |
JP (1) | JPS6321280B2 (de) |
DE (1) | DE2967321D1 (de) |
WO (1) | WO1980000632A1 (de) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4281398A (en) * | 1980-02-12 | 1981-07-28 | Mostek Corporation | Block redundancy for memory array |
CA1168377A (en) * | 1980-04-25 | 1984-05-29 | Michael L. Ziegler | Data processing system having a memory system which utilizes a cache memory and unique pipelining techniques for providing access thereto |
US4471243A (en) * | 1982-07-26 | 1984-09-11 | Rca Corporation | Bidirectional interface |
US4535428A (en) * | 1983-03-10 | 1985-08-13 | International Business Machines Corporation | Multi-port register implementations |
US4616347A (en) * | 1983-05-31 | 1986-10-07 | International Business Machines Corporation | Multi-port system |
US4558433A (en) * | 1983-05-31 | 1985-12-10 | International Business Machines Corporation | Multi-port register implementations |
US4577292A (en) * | 1983-05-31 | 1986-03-18 | International Business Machines Corporation | Support circuitry for multi-port systems |
US4577293A (en) * | 1984-06-01 | 1986-03-18 | International Business Machines Corporation | Distributed, on-chip cache |
US4823324A (en) * | 1985-09-23 | 1989-04-18 | Ncr Corporation | Page mode operation of main system memory in a medium scale computer |
JPS62287499A (ja) * | 1986-06-06 | 1987-12-14 | Fujitsu Ltd | 半導体メモリ装置 |
JPH01100788A (ja) * | 1987-10-13 | 1989-04-19 | Hitachi Ltd | 半導体集積回路装置 |
US6112287A (en) * | 1993-03-01 | 2000-08-29 | Busless Computers Sarl | Shared memory multiprocessor system using a set of serial links as processors-memory switch |
US5086388A (en) * | 1988-03-18 | 1992-02-04 | Hitachi Maxell, Ltd. | Semiconductor serial/parallel-parallel/serial file memory and storage system |
JP2923786B2 (ja) * | 1988-03-18 | 1999-07-26 | 日立マクセル株式会社 | 半導体ファイルメモリ及びそれを用いる記憶システム |
IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
US5995443A (en) * | 1990-04-18 | 1999-11-30 | Rambus Inc. | Synchronous memory device |
US6810449B1 (en) | 1995-10-19 | 2004-10-26 | Rambus, Inc. | Protocol for communication with dynamic memory |
US6470405B2 (en) * | 1995-10-19 | 2002-10-22 | Rambus Inc. | Protocol for communication with dynamic memory |
US5949254A (en) * | 1996-11-26 | 1999-09-07 | Micron Technology, Inc. | Adjustable output driver circuit |
US5838177A (en) * | 1997-01-06 | 1998-11-17 | Micron Technology, Inc. | Adjustable output driver circuit having parallel pull-up and pull-down elements |
US6266379B1 (en) | 1997-06-20 | 2001-07-24 | Massachusetts Institute Of Technology | Digital transmitter with equalization |
US6401167B1 (en) * | 1997-10-10 | 2002-06-04 | Rambus Incorporated | High performance cost optimized memory |
WO1999019805A1 (en) | 1997-10-10 | 1999-04-22 | Rambus Incorporated | Method and apparatus for two step memory write operations |
US6178532B1 (en) * | 1998-06-11 | 2001-01-23 | Micron Technology, Inc. | On-chip circuit and method for testing memory devices |
US6675272B2 (en) * | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
US8391039B2 (en) * | 2001-04-24 | 2013-03-05 | Rambus Inc. | Memory module with termination component |
US7301831B2 (en) * | 2004-09-15 | 2007-11-27 | Rambus Inc. | Memory systems with variable delays for write data signals |
US9672169B2 (en) * | 2010-06-30 | 2017-06-06 | Texas Instruments Incorporated | Dual in line memory module with multiple memory interfaces |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3969706A (en) * | 1974-10-08 | 1976-07-13 | Mostek Corporation | Dynamic random access memory misfet integrated circuit |
US4024512A (en) * | 1975-06-16 | 1977-05-17 | Fairchild Camera And Instrument Corporation | Line-addressable random-access memory |
JPS5240035A (en) * | 1975-09-25 | 1977-03-28 | Nippon Telegr & Teleph Corp <Ntt> | Memory equipment using electric charge transfer element |
US4159541A (en) * | 1977-07-01 | 1979-06-26 | Ncr Corporation | Minimum pin memory device |
-
1978
- 1978-09-01 US US05/939,297 patent/US4183095A/en not_active Expired - Lifetime
-
1979
- 1979-08-28 JP JP54501517A patent/JPS6321280B2/ja not_active Expired
- 1979-08-28 WO PCT/US1979/000675 patent/WO1980000632A1/en unknown
- 1979-08-28 DE DE7979901181T patent/DE2967321D1/de not_active Expired
-
1980
- 1980-04-08 EP EP79901181A patent/EP0016827B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0016827A4 (de) | 1981-10-27 |
WO1980000632A1 (en) | 1980-04-03 |
EP0016827B1 (de) | 1984-12-05 |
EP0016827A1 (de) | 1980-10-15 |
JPS6321280B2 (de) | 1988-05-06 |
JPS55500611A (de) | 1980-09-04 |
US4183095A (en) | 1980-01-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE2967321D1 (en) | High density memory system | |
DE3176824D1 (en) | High density memory system | |
JPS558696A (en) | Nonnvolatile memory | |
JPS5567949A (en) | Memory carrier | |
JPS54124941A (en) | Memory system | |
JPS54162934A (en) | Read only memory | |
JPS5552274A (en) | Nonnvolatile memory | |
JPS5517896A (en) | Dynamic memory storage sub system | |
JPS54159827A (en) | Memory circuit | |
JPS5525895A (en) | Memory system | |
GB2022355B (en) | Special effects memory system | |
JPS5589968A (en) | Memory system | |
JPS5587385A (en) | Memory cell | |
GB2016772B (en) | Data storage | |
JPS54132136A (en) | Memory system | |
JPS54117641A (en) | Memory inspecting system | |
JPS54142925A (en) | Memory | |
JPS567291A (en) | Memory operating system | |
DE2967586D1 (en) | Row-column-addressable memory with serial-parallel-serial configuration | |
EP0032136A3 (en) | Memory system | |
GB2014767B (en) | Memory devices | |
JPS5580874A (en) | Storage hierarchy system | |
JPS567292A (en) | Dsemiconductor memory | |
JPS5683884A (en) | Multiiaccess memory | |
JPS5577087A (en) | Memory unit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8320 | Willingness to grant licences declared (paragraph 23) | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NCR INTERNATIONAL INC., DAYTON, OHIO, US |
|
8328 | Change in the person/name/address of the agent |
Free format text: KAHLER, K., DIPL.-ING., 8948 MINDELHEIM KAECK, J., DIPL.-ING. DIPL.-WIRTSCH.-ING., 8910 LANDSBERG FIENER, J., PAT.-ANWAELTE, 8948 MINDELHEIM |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR |
|
8339 | Ceased/non-payment of the annual fee |