DE2704833A1 - Conductive path end region for soldering to semiconductor element - consists of narrow insertable section for terminal contact with adjacent wide reservoir section - Google Patents

Conductive path end region for soldering to semiconductor element - consists of narrow insertable section for terminal contact with adjacent wide reservoir section

Info

Publication number
DE2704833A1
DE2704833A1 DE19772704833 DE2704833A DE2704833A1 DE 2704833 A1 DE2704833 A1 DE 2704833A1 DE 19772704833 DE19772704833 DE 19772704833 DE 2704833 A DE2704833 A DE 2704833A DE 2704833 A1 DE2704833 A1 DE 2704833A1
Authority
DE
Germany
Prior art keywords
area
semiconductor element
end region
soldering
conductor track
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19772704833
Other languages
German (de)
Other versions
DE2704833C2 (en
Inventor
Horst-Joachim Dipl Ph Hartmann
Walter Dipl Ing Keefer
Wolfgang Dipl Phys D Leibfried
Karl Rampmaier
Wolfgang Dipl Phys Schynoll
Guenter Dipl Phys Stecher
Klaus Steinle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE2704833A priority Critical patent/DE2704833C2/en
Publication of DE2704833A1 publication Critical patent/DE2704833A1/en
Application granted granted Critical
Publication of DE2704833C2 publication Critical patent/DE2704833C2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10234—Metallic balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10992—Using different connection materials, e.g. different solders, for the same connection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/042—Remote solder depot on the PCB, the solder flowing to the connections from this depot
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

The conductive path end region is intended for a hybrid circuit, and serves for soldering of a semiconductor element (5) according to reflow solder process in flip-chip technique. The end region consists of a narrow, finger-shaped inserting region (2b) for the terminal contact of the semiconductor element and an adjacent wider reservoir region (2a) for the excessive molten solder. The width of the reservoir region, between the inserting region and the conductive path proper (2), is about three times that of the finger-shaped inserting region. Typically the latter is 0.2 mm wide and 0.6 mm long, while the reservoir region is a square of 0.6 mm. The conductive path is 0.3 mm wide.

Description

Leiterbahn-Endbereich zum Anlöten eines HalbleiterelementesConductor track end area for soldering a semiconductor element

in Flip-Chip-Technik Zusammenfassung Es wird ein Leiterbahn-Endbereich für eine Hybridschaltung zum Anlöten eines Halbleiterelementes in Flip-Ghip-Technik nach dem Reflow-Solder-Verfahren vorgeschalagen.Der Leiterbahn-Endbereich besteht aus einem schmalen, fingerförmigen Aufsetzgebiet für den Anschlußkontakt des Flip-Chip-Elementes und aus einem sich daran anschließenden breiteren Reservoirgebiet für überschüssiges aufgeschmolzenes Lot.in flip-chip technology Summary A conductor track end area is created for a hybrid circuit for soldering a semiconductor element using flip-chip technology according to the reflow soldering process from a narrow, finger-shaped contact area for the connection contact of the flip-chip element and from an adjoining wider reservoir area for excess melted solder.

Stand der Technik Die Erfindung geht aus von einem Leiterbahn-Endbereich nach der Gattung des Hauptanspruchs. Bei der Montage von lötbaren Flip-Chip-Halbleiterelementen in elecktronischen Dickschicht-oder Dünnfilmschaltungen werden diese Elemente mit ihren Anschlußkontakten, die mit Weichlot belegt sind, in die Leiterbahnstructuren der Schaltungen eingelötet. Dabei setzen die Anschlußkontakte der Halbleiterelement auf entsprechend angeordnete Leiterbahn-Endbereiche auf, die Bestandteil der elektronischen Dickschicht- oder Dünnfilmschaltung sind. Diese Leiterbahn-Endbereiche werden gewöhnlich vor dem Aufsetzen der Ilip-Chip-Elemente in einem getrennten Arbeitsgang mit schmelzflüssigem Weichlot überzogen, so daß das eigentliche Einlöten der Flip-Chip-Elemente nach dem Reflow-Solder-Prinzip erfolgt, bei dem beide Lötpartner beim Zusammenfügen mit genügend dicken Lotfilmen überzogen sind, so daß bein Zusammenlöten kein weiteres Lot mehr hinzugefügt zu werden braucht.PRIOR ART The invention is based on a conductor track end area according to the genre of the main claim. When assembling solderable flip-chip semiconductor elements these elements are used in electronic thick-film or thin-film circuits their connection contacts, which are covered with soft solder, in the conductor track structures of the circuits soldered in. The connection contacts of the semiconductor element set on appropriately arranged conductor track end regions, which are part of the electronic Thick film or thin film circuit are. These trace ends become common before placing the Ilip-Chip elements in a separate operation with molten liquid Soft solder coated so that the actual soldering of the flip-chip elements after the reflow solder principle takes place, in which both soldering partners with the joining together sufficiently thick solder films are coated so that no further soldering is required Lot more needs to be added.

Das Aufbringen von schmelzflüssigem Lot auf die Leiterbahn-Endbereiche ist gegenüber anderen Auftragungsverfahren - wie beispielsweise galvanische Abscheidung oder dergleichen - besonders eiijfaeh durchzuführen und auch von großem Vorteil für die Qualität der resultierenden Lötverbindung zwischen Flip-Chip-Eleinent und elektronischer Schaltung. Das Beschichten der Leiterbahn-Endbereiche mit dem schmelzflüssigen Lot erfolgt dabei zweckmäßigerweise nach dem Schwall- (Lotwelle) oder Tauch-Verfahren (ruhendes Lotbad) Bei den bekannten Hybridschaltungen, die in Flip-Chip-Ausführung hergestellt sind, hat es sich nun gezeigt, daß die Lotfilme, die auf den zum Anlöten der Halbleiterelemente dienenden Leiterbahn-Enbereichen aufgeschmolzen sind, nicht von konstanter Dicke sind, obwohl bereits Maßnahmen bekanntgeworden sind, die darauf abzielen, diese Dicke möglichst konstant zu halten.The application of molten solder to the trace end regions is compared to other application methods - such as galvanic deposition or the like - especially easy to carry out and also of great advantage for the quality of the resulting soldered connection between the flip-chip element and electronic circuit. The coating of the conductor track end areas with the molten Solder is expediently carried out using the surge (solder wave) or immersion method (static solder bath) In the known hybrid circuits, which are in flip-chip design Are produced, it has now been shown that the solder films that are on the for soldering the conductor track end areas serving semiconductor elements are not melted are of constant thickness, although measures have already become known that on it aim to keep this thickness as constant as possible.

Vorteile der Erfindung Der erfindungsgemäße Leiterbahn-Endbereich mit den kennzeichnenden Merkmalen des Hauptanspruchs hat demgegenüber den Vorteil, daß die Lotfilmdicke im Aufsetzgebiet des Anschlußkontaktes des Flip-Chip-Halbleiterelementes sehr konstant ist und nur eine sehr geringe Streubreite hat. Weiterbildungen der Erfindung ergeben sich aus den Unteransprüchen 2 bis 4.Advantages of the Invention The conductor track end region according to the invention with the characterizing features of the main claim has the advantage over this that the solder film thickness in the contact area of the connection contact of the flip-chip semiconductor element is very constant and has only a very small spread. Further training of the The invention emerges from the subclaims 2 to 4.

Zeichnung Ein AusfüIrungsbeispiel der Erfindung ist in der Zeichnung dargestellt und iri der nachfolgenden Beschreibung näher erläutert. Figur 1 zeigt eine Draufsicht auf einen Leiterbahnzug, der in einen Leiterbahn-Endbereich gemäß der Erfindung ausläuft, Figur 2 eine Seitenansicht der gleichen Verbindungsstelle mit einem aufgesetzten Flip-Chip-Halbleiterelement, jedoch vor dem Erhitzen auf Löttemperatur, teilweise im Schnitt, teilweise abgebrochen.Drawing An exemplary embodiment of the invention is shown in the drawing and explained in more detail in the following description. Figure 1 shows a plan view of a conductor track, which is in a conductor track end area according to the invention expires, Figure 2 is a side view of the same connection point with an attached flip-chip semiconductor element, but before heating Soldering temperature, partly in the cut, partly broken off.

Beschreibung der Erfindung Gemäß Figur 1 ist auf einem nichtleitenden Substrat 1 ein Leiterbahnzug 2 angeordnet. In seinem Endbereich erweitert sich der Leiterbahnzug 2 zuerst zu einem etwa quadratischen Reservoirgebiet 2a, um sich anschließend zu dem fingerförmigen Gebiet 2b zu verschinälern, das als Aufsetzgebiet für den Anschlußkontakt des Flip-Ghip-Halbleiterelementes dient.Description of the invention According to Figure 1 is on a non-conductive Substrate 1, a strip conductor 2 is arranged. In its end area the expands Conductor track 2 first to an approximately square reservoir area 2a, to then to shrink to the finger-shaped area 2b, which is used as a touchdown area for the Terminal contact of the flip-chip semiconductor element is used.

In Figur 2 erkennt man auf dem nichtleitenden Substrat 1 den in den Endbereich 2a, 2b auslaufenden Leiterbahnzug 2, auf dem sich eine Lotschicht 3 ausgebildet hat. Über dem Aufsetzgebiet 2b wurde ein Anschlußkontakt 6 eines Halbleiterelementes 5 positioniert. Der Anschlußkontakt G des Halbleiterelementes 5 besteht aus einem harten, beim Lötprozeß nicht schmelzenden Kern 6a, beispielsweise aus Kupfer, und aus einer auf den Kern aufgebrachten Weichlotschicht 6b, beispielsweise aus Blei oder Zinn, die dem Aufsetzgebiet 2b zugekehrt ist.In Figure 2 can be seen on the non-conductive substrate 1 in the End area 2a, 2b terminating conductor track 2, on which a solder layer 3 is formed Has. A connection contact 6 of a semiconductor element was placed above the contact area 2b 5 positioned. The connection contact G of the semiconductor element 5 consists from a hard core 6a which does not melt during the soldering process, for example Copper, and a soft solder layer 6b applied to the core, for example made of lead or tin, which faces the contact area 2b.

Die Wirkungsweise des erfindungsgemäß ausgestalteten Leiterbahn-Endbereichs 2a, 2b ist folgende: Nach dem Aufbringen des schmelzflüssigen Lotes 3 im Schwall- bzw. Tauchverfahren zeigt sich, daß die Lotfilmdicke im Aufsetzgebiet 2b des Anschlußkontakts 6 des Plip-Chip-llalbleiterelementes 5 sehr konstant ist und nur eine sehr kleine Streubreite hat, während sie im Reservoirgebiet 2a weit weniger konstant ist und ziemlich breit streut. Die sonst als statistische Streubreite auftretende Dickenvariation von Lotfilmen auf Leiterbahnen ist also durch die erfindungsgemäße geometrische Formgebung von dem schmalen, fingerförmigen Bereich 2b der Leiterbahn, der als Aifsetzgebiet dient, in das sich anschließende Reservoir-Gebict 2a verlagert worden, wo sie für die Flip-Chip-Kontaktierung keine Rolle spielt und nicht stört. Die Lotfilmdicke auf dem fingerförmigen Aufsetzgebiet 2b der Leiterbahn 2 hat also die gewünschte und geforderte notwendige Gleichmäßigkeit.The mode of operation of the conductor track end region designed according to the invention 2a, 2b is the following: After applying the molten solder 3 in the surge or immersion method shows that the solder film thickness in the contact area 2b of the terminal contact 6 of the plug-chip semiconductor element 5 is very constant and only a very small one Has spread, while it is far less constant in the reservoir area 2a and spreads quite widely. The thickness variation that otherwise occurs as a statistical spread of solder films on conductor tracks is thus through the inventive geometric Shaping of the narrow, finger-shaped area 2b of the conductor track, which is used as a setting area has been relocated to the adjoining reservoir area 2a, where it is used for the flip-chip contact is irrelevant and does not interfere. The solder film thickness on the finger-shaped contact area 2b of the conductor track 2 thus has the desired and required uniformity.

Das Zustandekommen dieses Effektes wird in erster Linie durch die Oberflächenspannung des flüssigen Lotes und die Grenzflächenspannung zwischen der Metallisierung und dem Lot bewirkt. Bei vorgegebener konstanter Metallisierungsart bestimmt also die Oberflächenspannung des Lotes zusammen mit der Breite des fingerförmigen Bereiches 2b der Leiterbahn 2 die Dicke des flüssigen Lotfilmes, die sich in diesem Aufsetzgebiet einstelletj kann. Alles flüssige Lot, das im Sinne dieser Gesetzmäßigkeit zu viel oder zu wenig im fingerförmigen Aufsetzgebiet 2b vorhanden ist, wird in das Reservoirgebiet 2a abgeschoben bzw. von dort herausgeholt. Für die Dickenkonstanz des resultierenden Lotfilmes ist dabei die zeitliche und örtliche Konstanz der Oberflächenspannung des flüssigen Lotes die wichtigste Voraussetzung Diese experimentelle Bedingung ist besonders dann sehr gut gegeben, wenn das Aufschmelzen des Lotfilmes im Schwallverfahren unter Schutzgas in reduzierender Atmosphäre (kein Sauerstoff anwesend) und ohne Anwendung von Flußmitteln erfolgt (sehr reines Lot, frei von nichtmetallischen Beimengungen) Beim Ausführungsbeispiel n'ieii den Figuren 1 und 2 hat das fingerförmige Aufsetzgebiet 2b eine Breite von 0,2 mm und eine Länge von 0,6 mm. Das Reservoirgebiet 2a hat eine Breite von 0,6 mm und eine Länge von 0,6 mm, wahrend der Leiterbahnzug 2, der zur Verbindung des Endbereichs 2a, 2b mit dem Leiterbahnnetzwerk der Schaltung dient, eine Breite von 0,3 mm hat.This effect is primarily due to the Surface tension of the liquid solder and the interfacial tension between the Metallization and the solder causes. With a given constant type of metallization thus determines the surface tension of the solder together with the width of the finger-shaped Area 2b of the conductor track 2, the thickness of the liquid solder film, which is in this Contact area can be adjusted. All liquid solder in the sense of this law too much or too little is present in the finger-shaped contact area 2b, it is shown in the reservoir area 2a pushed off or retrieved from there. For constant thickness of the resulting solder film is the temporal and spatial constancy of the surface tension of the liquid solder main requirement This experimental The condition is particularly good when the solder film melts in a surge process under protective gas in a reducing atmosphere (no oxygen present) and without the use of flux (very pure solder, free of non-metallic admixtures) In the exemplary embodiment shown in FIGS 2, the finger-shaped contact area 2b has a width of 0.2 mm and a length of 0.6 mm. The reservoir area 2a has a width of 0.6 mm and a length of 0.6 mm, while the strip conductor 2, which is used to connect the end region 2a, 2b with the Conductor network serving the circuit, has a width of 0.3 mm.

Der Leiterbahnzug 2 mit seinem Endbereich 2a, 2b besteht vorteilhaft aus Nickel. Unter der Nickelschicht 2 kann sich eine in der Zeichnung nicht dargestellte Tantalschicht befinden, falls die gesamte Anordnung als elektronische Dünnfilmschaltung ausgeführt ist.The strip conductor 2 with its end region 2a, 2b is advantageous made of nickel. A not shown in the drawing can be located under the nickel layer 2 Tantalum layer, if the entire arrangement is a thin-film electronic circuit is executed.

Die Anordnung kann aber auch als sogenannte "gedruckte Leiterplatte" ausgeführt sein. Dann besteht der Leiterbahnzug 2 mit seinem Endbereich 2a, .'b aus Kupfer, und eine Tantalsehietit ist nicht vorhanden.The arrangement can also be used as a so-called "printed circuit board" be executed. Then there is the strip conductor 2 with its end region 2a, .'b made of copper, and a tantalum sehietite is not present.

Claims (4)

A n s p r ü c h e 1. Leiterbahn-Endbereich für eine Hybridschaltung zum Anlöten eines Halbleiterelementes (5) in Flip-Chip-Technik nach dem Reflow-Solder-Verfahren, dadurch gekennzeichnet, daß er aus einem schmalen, fingerförmigen Atifsetzgcbiet (2b) für den Anschlußkontakt (6) des Flip-Chip-Elementes (5) und aus einem sich daran anschließenden breiteren Reservoirgebiet (2a) für überschüssiges aufgeschmolzenes Lot besteht. A n p r ü c h e 1. Conductor track end area for a hybrid circuit for soldering a semiconductor element (5) using flip-chip technology using the reflow soldering process, characterized in that it consists of a narrow, finger-shaped Atifsetzgciet (2b) for the connection contact (6) of the flip-chip element (5) and from one itself adjoining wider reservoir area (2a) for excess melted Lot exists. 2. Leiterbahn-Endbereich nach Anspruch 1, dadurch gekennzeichnet, daß das Reservoirgebiet (2a) zwischen dem Aufsetzgebiet (2b) und dem Leiterbahnzug (2) angeordnet ist, der zur Verbindung des Endbereiches (2a, 2b) mit dem Leitbahnnetzwcrk der Schaltung dient. 2. conductor track end region according to claim 1, characterized in that that the reservoir area (2a) between the touchdown area (2b) and the strip conductor (2) is arranged to connect the end region (2a, 2b) to the interconnect network the circuit is used. 3. Leiterbahn-Endbereich nach Anspruch 2, dadurch gekennzeichnet, daß die Breite des Reservoirgcbietes (2a) etwa dreimal so groß ist wie die Breite des fingerförmigen Aufsetzgebietes (2b). 3. conductor track end region according to claim 2, characterized in that that the width of the reservoir area (2a) is about three times as large as the width the finger-shaped touchdown area (2b). 4. Leiterbahn-Endbcreich nach Anspruch 3, dadurch gekennzeichnet, daß das fingerforlllige Aufsetzgebiet (2b) 0,2 mm breit und 0,6 nun lang und das Reservoirgebiet (2a) 0,6 mm lang und 0,6 mm breit ist, während der Leiterbahnzug (2) eine Breite von 0,3 mm hat. 4. conductor track end area according to claim 3, characterized in that that the finger-shaped contact area (2b) 0.2 mm wide and 0.6 now long and that Reservoir area (2a) is 0.6 mm long and 0.6 mm wide, while the conductor track (2) has a width of 0.3 mm.
DE2704833A 1977-02-05 1977-02-05 Conductor track end area for soldering a semiconductor element using flip-chip technology Expired DE2704833C2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE2704833A DE2704833C2 (en) 1977-02-05 1977-02-05 Conductor track end area for soldering a semiconductor element using flip-chip technology

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2704833A DE2704833C2 (en) 1977-02-05 1977-02-05 Conductor track end area for soldering a semiconductor element using flip-chip technology

Publications (2)

Publication Number Publication Date
DE2704833A1 true DE2704833A1 (en) 1978-08-17
DE2704833C2 DE2704833C2 (en) 1982-05-27

Family

ID=6000439

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2704833A Expired DE2704833C2 (en) 1977-02-05 1977-02-05 Conductor track end area for soldering a semiconductor element using flip-chip technology

Country Status (1)

Country Link
DE (1) DE2704833C2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0084464A2 (en) * 1982-01-20 1983-07-27 North American Specialities Corporation Connector for electronic subassemblies
US20170141072A1 (en) * 2015-11-13 2017-05-18 International Business Machines Corporation Optimized solder pads for microelectronic components

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2157956A1 (en) * 1970-11-24 1972-05-31 Lucas Ltd Joseph Method for electrically connecting a semiconductor chip to a substrate
DE2307325B2 (en) * 1973-02-14 1975-09-04 Siemens Ag, 1000 Berlin Und 8000 Muenchen Layer circuit with at least one soldering platform for soldering semiconductor components

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2157956A1 (en) * 1970-11-24 1972-05-31 Lucas Ltd Joseph Method for electrically connecting a semiconductor chip to a substrate
DE2307325B2 (en) * 1973-02-14 1975-09-04 Siemens Ag, 1000 Berlin Und 8000 Muenchen Layer circuit with at least one soldering platform for soldering semiconductor components

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"IBM Technical Disclosure Bulletin", Bd. 16, Nr. 8 (Jan. 1974), S. 2675 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0084464A2 (en) * 1982-01-20 1983-07-27 North American Specialities Corporation Connector for electronic subassemblies
EP0084464A3 (en) * 1982-01-20 1985-09-18 North American Specialities Corporation Connector for electronic subassemblies
US20170141072A1 (en) * 2015-11-13 2017-05-18 International Business Machines Corporation Optimized solder pads for microelectronic components
US10014274B2 (en) * 2015-11-13 2018-07-03 International Business Machines Corporation Optimized solder pads for microelectronic components

Also Published As

Publication number Publication date
DE2704833C2 (en) 1982-05-27

Similar Documents

Publication Publication Date Title
DE69204516T2 (en) Printed circuit board with solder coating and process for its manufacture.
DE69022605T2 (en) Electrical connection device.
DE4126913A1 (en) METHOD FOR SOLDERING AND ASSEMBLING PCBS WITH COMPONENTS
DE3824008A1 (en) ELECTRONIC CIRCUIT AND METHOD FOR THE PRODUCTION THEREOF
DE3042085A1 (en) SEMICONDUCTOR BOARD ASSEMBLY AND METHOD FOR THE PRODUCTION THEREOF
EP0487782B1 (en) Method of soldering circuit boards
DE69704678T2 (en) METHOD FOR PRODUCING A TIN / LEAD LAYER PCB ASSEMBLY
DE1943519A1 (en) Semiconductor component
DE2839110C2 (en) Method of applying fusible solder balls to the surface of an insulating substrate
DE60102115T2 (en) Method and device for wave soldering
DE69215377T2 (en) MELTING SOLDERING PROCESS FOR FORMING A SOLDERING STICK ON A PRINT PLATE
EP1080615B1 (en) Multiple printed panel for electronics components, and method for constructing bumps, soldering frames, spacers and similar on said multiple printed panel.
DE19622971A1 (en) Semiconductor device for SMT and mfg. method
DE3881378T2 (en) Method for making a through electrical connection using a solderable mechanical holder.
DE3211408C2 (en)
DE2528000B2 (en) Method for producing a soldering surface of relatively large dimensions
DE2704833A1 (en) Conductive path end region for soldering to semiconductor element - consists of narrow insertable section for terminal contact with adjacent wide reservoir section
DE69328211T2 (en) Installation of electronic components on mounting plates using reflow technology
DE4036079A1 (en) ELECTRONIC COMPONENT AND ELECTRONIC DEVICE WITH SUCH A COMPONENT
DE9015206U1 (en) Resistor arrangement in SMD design
EP0090820B1 (en) Thin layered electronic circuit and manufacturing method thereof
DE3235717C2 (en) Connection element for a circuit board
DE1465736A1 (en) Process for the production of function blocks, especially for data processing systems
DE102019129971A1 (en) Method for soldering a component onto a printed circuit board, electronic unit and field device in automation technology
EP0144413A1 (en) Printed board for the surface soldering of integrated miniature circuits and manufacturing method of such printed boards

Legal Events

Date Code Title Description
OD Request for examination
8125 Change of the main classification

Ipc: H01L 23/48

D2 Grant after examination
8363 Opposition against the patent
8339 Ceased/non-payment of the annual fee