DE2406451C3 - Trigger circuit for suppressing interference amplitudes in strongly disturbed signals - Google Patents
Trigger circuit for suppressing interference amplitudes in strongly disturbed signalsInfo
- Publication number
- DE2406451C3 DE2406451C3 DE19742406451 DE2406451A DE2406451C3 DE 2406451 C3 DE2406451 C3 DE 2406451C3 DE 19742406451 DE19742406451 DE 19742406451 DE 2406451 A DE2406451 A DE 2406451A DE 2406451 C3 DE2406451 C3 DE 2406451C3
- Authority
- DE
- Germany
- Prior art keywords
- transistor
- input
- amplitude
- trigger
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000001629 suppression Effects 0.000 title claims description 4
- 239000003990 capacitor Substances 0.000 claims description 12
- 230000001808 coupling Effects 0.000 claims description 11
- 238000010168 coupling process Methods 0.000 claims description 11
- 238000005859 coupling reaction Methods 0.000 claims description 11
- 241000158147 Sator Species 0.000 claims 1
- 230000003321 amplification Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 230000000875 corresponding Effects 0.000 claims 1
- 230000002452 interceptive Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
- 230000002123 temporal effect Effects 0.000 claims 1
Description
des Ausgangstransistors T2 wird gegen + UB gezogen. Über den Widerstand A6 erfolgt eine Mitkopplung, indem dieser Potentialsprung der Basis des Eingangstransistors T1 mitgeteilt wird. Nach dem Abfall der Eingangsampiitude unter den Triggerpegel wird der Steuerstrom des Transistors T1 unterbrochen, und der Kollektor des Ausgangstransistors T2 geht wieder in die Ausgangslage, d. h., er befindet sich etwa auf dem Bezugspotential. Diese Verhältnisse gthen aus Fig. Ib hervor. Der Koppelkondensator C1 bleibt jedoch aufgeladen, da die Basis-Emitter-Diode des Eingangstransistors T1 nunmehr sperrt. Eine langsame Entladung des Koppelkondensators erfolgt lediglich über die Widerstände A1 und Re. Damit hat die Basis des Eingangstransistors T1 eine negativeof the output transistor T 2 is pulled towards + U B. A positive feedback takes place via the resistor A 6 , in that this potential jump is communicated to the base of the input transistor T 1. After the input amplitude has dropped below the trigger level, the control current of transistor T 1 is interrupted and the collector of output transistor T 2 returns to its initial position, ie it is approximately at reference potential. These relationships emerge from Fig. Ib. The coupling capacitor C 1 remains charged, however, since the base-emitter diode of the input transistor T 1 is now blocked. The coupling capacitor is only slowly discharged via the resistors A 1 and R e . So that the base of the input transistor T 1 has a negative
Vorspannung, deren Größe entsprechend der vorherigen Amplitude ist Eine nunmehr auftretende Störung muß zunächst einmal die zu dem betreffenden Zeitpunkt noch anstehende Vorspannung am Koppelkondensator C1 überschreiten, ehe sie den Eingangstransistor T1 durchschalten kann. Legt man die Zeitkonstante τ — bestimmt durch den Kopplungskondensator C1 und die Widerstände A1 und Re — so aus, daß bis zur nächsten Nutzamplitude z. B. nur X= 10% Ladungsverluste auftreten können, so kann in der Impulspause mit Sicherheit mit einem Störabstand von Y = 90% gerechnet werden. Dies bedeutet, daß alle Störamplituden B1, B2, die bis zu 90% der Nutzamplituden A1, A2 betragen dürfen, unterdrückt werden.Bias voltage, the magnitude of which corresponds to the previous amplitude. A disturbance that now occurs must first of all exceed the bias voltage that is still present at the coupling capacitor C 1 at the time in question before it can switch through the input transistor T 1. If one interprets the time constant τ - determined by the coupling capacitor C 1 and the resistors A 1 and R e - so that up to the next useful amplitude z. If, for example, only X = 10% charge losses can occur, a signal-to-noise ratio of Y = 90% can be expected with certainty in the pulse pause. This means that all interference amplitudes B 1 , B 2 , which may be up to 90% of the useful amplitudes A 1 , A 2 , are suppressed.
Hierzu 1 Blatt Zeichnungen1 sheet of drawings
Claims (5)
ohmigen Widerstand (/?„) mit dem Kollektor des as An Hand der Figuren der Zeichnung wird ein Ausgangstransistors (T2) verbunden ist. Ausführungsbeispiel der Erfindung im folgenden2. Trigger circuit according to claim 1 with two 20 depending on the absolute size of the input transistors of the same conductivity type, which signal is. The solution of this object is achieved through a resistor direct current gekop- by as characterized in claim 1 this invention are pelt, characterized in that the base Further advantageous embodiments of the invention, the input transistor (T 1) via a high are removed in the subclaims,
ohmic resistance (/? „) with the collector of the as On the basis of the figures of the drawing an output transistor (T 2 ) is connected. Embodiment of the invention in the following
transistors (T2) verbunden ist. Fig. 2 eine Schaltungsanordnung gemäß der Er-Resistance (R 1 ) to the emitter of the output 30 output signal,
transistor (T 2 ) is connected. Fig. 2 shows a circuit arrangement according to the
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19742406451 DE2406451C3 (en) | 1974-02-11 | Trigger circuit for suppressing interference amplitudes in strongly disturbed signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19742406451 DE2406451C3 (en) | 1974-02-11 | Trigger circuit for suppressing interference amplitudes in strongly disturbed signals |
Publications (3)
Publication Number | Publication Date |
---|---|
DE2406451A1 DE2406451A1 (en) | 1975-08-14 |
DE2406451B2 DE2406451B2 (en) | 1976-05-13 |
DE2406451C3 true DE2406451C3 (en) | 1976-12-30 |
Family
ID=
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