DE220233T1 - CALIBRATION POINTS FOR ALIGNING A WAFER TEST HEAD. - Google Patents

CALIBRATION POINTS FOR ALIGNING A WAFER TEST HEAD.

Info

Publication number
DE220233T1
DE220233T1 DE1986902664 DE86902664T DE220233T1 DE 220233 T1 DE220233 T1 DE 220233T1 DE 1986902664 DE1986902664 DE 1986902664 DE 86902664 T DE86902664 T DE 86902664T DE 220233 T1 DE220233 T1 DE 220233T1
Authority
DE
Germany
Prior art keywords
key
chip
key means
improved
mutually parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE1986902664
Other languages
German (de)
Inventor
Horst Phoenix Az 85023 Leuschner
Original Assignee
Sgs Semiconductor Corp., Phoenix, Ariz.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Semiconductor Corp., Phoenix, Ariz. filed Critical Sgs Semiconductor Corp., Phoenix, Ariz.
Priority claimed from PCT/US1986/000698 external-priority patent/WO1986006176A1/en
Publication of DE220233T1 publication Critical patent/DE220233T1/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)

Claims (4)

AnsprücheExpectations 1. Verbessertes System von Ausrichtungsschlüsseln für Halbleiter-Chips, gekennzeichnent durch eine erste Schlüsseleinrichtung zum Pestlegen einer ersten X- und Y-Koordinatenstelle auf dem Chip, wobei sich die erste Schlüsseleinrichtung innerhalb einer Fläche befindet, die durch einen Satz von vier Ritzlinien für diesen Chip definiert ist; eine zweite Schlüsseleinrichtung zum Festlegen einer zweiten X- und Y-Koordinatenstelle auf dem Chip, wobei sich die zweite Schlüsseleinrichtung innerhalb der Fläche befindet, die durch den Satz von vier Ritzlinien für diesen Chip definiert ist; und durch eine dritte Schlüsseleinrichtung zum Festlegen einer dritten X- und Y-Koordinatenstelle auf dem Chip, wobei sich die dritte Schlüsseleinrichtung innerhalb der Fläche befindet, die durch den Satz von vier Ritzlinien für diesen Chip definiert ist, wobei die erste und die zweite Schlüsseleinrichtung derart angeordnet sind, daß eine durch den ersten und den zweiten Satz von X- und Y-Koordinaten gezogene gerade Linie im wesentlichen parallel zu sowie relativ nahe bei einer der Ritzlinien verläuft und sich der dritte Schlüsseleinrichtungssatz relativ nahe bei einer anderen Ritzlinie befindet, wobei die genannte andere Ritzlinie ; sowie die genannte eine Ritzlinie wesentlichen parallel zueinander sind und sich auf gegenüberliegenden Seiten des Chips befinden.1. An improved system of alignment keys for semiconductor chips, characterized by a first key means for specifying a first X and Y coordinate location on the chip, the first key means being located within an area defined by a set of four scribe lines for that chip; a second key means for specifying a second X and Y coordinate location on the chip, the second key means being located within the area defined by the set of four scribe lines for that chip; and by a third key means for defining a third X and Y coordinate location on the chip, the third key means being located within the area defined by the set of four scribe lines for that chip, the first and second key means being arranged such that a straight line drawn through the first and second sets of X and Y coordinates is substantially parallel to and relatively close to one of the scribe lines and the third set of key means is located relatively close to another scribe line, said another scribe line and said one scribe line being substantially parallel to each other and located on opposite sides of the chip. • t ·•t · 2. Verbessertes Schlüsselsystem nach Anspruch 1, dadurch gekennzeichnet,2. Improved key system according to claim 1, characterized in daß jede der Schlüsseleinrichtungen wenigstens einen Satz zueinander paralleler Schlüssel zum Festlegen einer X-Koordinate sowie wenigstens einen weiteren Satz zueinander paralleler Schlüssel zum Festlegen einer Y-Kpordinate umfaßt, wobei der genannte wenigstens eine Satz zueinander paralleler Schlüssel und der genannte wenigstens eine weitere Satz zueinander paralleler Schlüssel relativ nahe beieinander angeordnet sind.that each of the key devices comprises at least one set of mutually parallel keys for defining an X coordinate and at least one further set of mutually parallel keys for defining a Y coordinate, wherein said at least one set of mutually parallel keys and said at least one further set of mutually parallel keys are arranged relatively close to one another. 3. Verbessertes Schlüsselsystem nach Anspruch 1,3. Improved key system according to claim 1, dadurch gekennzeichnet, daß die erste Schlüsseleinrichtung und die zweite Schlüsseleinrichtung relativ weit voneinander beabstandet sind und die dritte Schlüsseleinrichtung von der ersten und der zweiten Schlüsseleinrichtung relativ weit entfernt ist.characterized in that the first key device and the second key device are relatively far apart from each other and the third key device is relatively far away from the first and second key devices. 4. Verbessertes Schlüsselsystem nach Anspruch 2, dadurch gekennzeichnet, daß die erste Schlüsseleinrichtung und die zweite Schlüsseleinrichtung relativ weit voneinander beabstandet sind und die dritte Schlüsseleinrichtung von der ersten und der zweiten Schlüsseleinrichtung relativ weit entfernt ist.4. Improved key system according to claim 2, characterized in that the first key device and the second key device are spaced relatively far apart from each other and the third key device is relatively far away from the first and second key devices.
DE1986902664 1985-04-08 1986-04-07 CALIBRATION POINTS FOR ALIGNING A WAFER TEST HEAD. Pending DE220233T1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72116685A 1985-04-08 1985-04-08
PCT/US1986/000698 WO1986006176A1 (en) 1985-04-08 1986-04-07 Target keys for wafer probe alignment

Publications (1)

Publication Number Publication Date
DE220233T1 true DE220233T1 (en) 1988-05-19

Family

ID=26773551

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1986902664 Pending DE220233T1 (en) 1985-04-08 1986-04-07 CALIBRATION POINTS FOR ALIGNING A WAFER TEST HEAD.

Country Status (1)

Country Link
DE (1) DE220233T1 (en)

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