DE2136509A1 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- DE2136509A1 DE2136509A1 DE19712136509 DE2136509A DE2136509A1 DE 2136509 A1 DE2136509 A1 DE 2136509A1 DE 19712136509 DE19712136509 DE 19712136509 DE 2136509 A DE2136509 A DE 2136509A DE 2136509 A1 DE2136509 A1 DE 2136509A1
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- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000009792 diffusion process Methods 0.000 claims description 86
- 239000000758 substrate Substances 0.000 claims description 65
- 239000012535 impurity Substances 0.000 claims description 34
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
- 230000000295 complement effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
- H01L29/1008—Base region of bipolar transistors of lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
Beschreibung zu der Patentanmeldung Halbleitervorrichtung Die Erfindung betrifft Halbleitervorrichtungen, insbesondere selbstausrichtende oder -abgleichende Diffusions-Metælloxyd-Siliziurn-fransistoren sowie ein Verfahren zu deren Herstellung. Description of the Patent Application Semiconductor Device The invention relates to semiconductor devices, particularly self-aligning or self-aligning ones Diffusion metal oxide silicon transistors and a process for their manufacture.
Metalloxyd-Silizium-Transistoren, im folgenden kurz als MOS-Transistoren bezeichnet, werden in der Technik in weitem Maße verwendet. Bei den bisher bekannten MOS-Transistoren bestehen Schwierigkeiten, die Kanallänge zwischen Source und Drain zu verkürzen, so daß bisher MOS-Transistoren mit höheren Schaltgeschwindigkeiten nicht realisierbar sind. Metal-oxide-silicon transistors, hereinafter referred to as MOS transistors for short are widely used in technology. With the previously known MOS transistors have difficulty adjusting the channel length between source and drain to shorten, so that so far MOS transistors with higher switching speeds are not feasible.
Der selbstausrichtende oder -abgleichende Diffusions-MOS-Transistor, im folgenden kurz als DSA-MOS-Transistor bezeichnet, ist ein verbessefter'MOS-Transtor mit verkürzter Kanallänge zwischen Source und Drain. Der DSA-MOS-Transistor zeichnet sich aus durch einen doppelten Diffusionsbereich, enthaltend einen Diffusionsbereich eines bestimmten Leitfähigkeitstyps, in dem ein weiterer Diffusionsbereich des entgegengesetzten Leitfahigkeitstyps mit Hilfe des sogenannten Doppel-Diffusionsver-tahrens ausgebildet ist. Der DSA-MOS-Iransistor enthält ein Halbleitersubstrat, eine auf dem Halbleitersubstrat ausgebildete Epitaxialschicht des dem des Substrats entgegengesetzten Leitfähigkeitstyps, eine auf der Epitaxialschicht in einer Tiefe bis zum Substrat ausgebildete Diffusionsschicht des Leitfähigkeitstyps des Substrats, und zwei in dem Diffusionsbereich und in der Epitaxialschicht ausgebildete Diffusionsschichten hoher Verunreinigungskonzentration, wobei der Leitfähigkeitstyp der erunreinigung,s-Diffusionsschicht dem des Substrats entgegengesetzt ist. Bei diesem DSA-MOS-Transitor liegt eine der Verunreinigungs-Diffusionsschichten angrenzend an die Epitaxialschicht. Die Epitaxialschicht wird üblicherweise in einer Halogene, beispielsweise Chlorgas enthaltenden Atmosphäre ausgebildet. Die Verwendung von Halogenen ftüirt jedoch zur Zerstörung oder Aufrauhung der Oberfläche der Epitaxialschicht, so daß es schwierig ist, Elemente mit glatter Oberfläche auf dem Substrat zu erzielen. The self-aligning or self-aligning diffusion MOS transistor, hereinafter referred to as DSA-MOS transistor for short, is an improved'MOS-Transtor with shortened channel length between source and drain. The DSA MOS transistor draws is made up of a double diffusion area containing a diffusion area of a certain conductivity type, in another diffusion area of the opposite conductivity type with the help of the so-called double diffusion method is trained. The DSA MOS transistor includes a semiconductor substrate, one on the epitaxial layer formed on the semiconductor substrate of the opposite to that of the substrate Conductivity type, one on the epitaxial layer at a depth to the substrate formed diffusion layer of the conductivity type of the substrate, and two in the diffusion region and diffusion layers formed in the epitaxial layer high impurity concentration, where the conductivity type of the impurity, s diffusion layer is opposite to that of the substrate. This DSA-MOS transistor has one of the Impurity diffusion layers adjacent the epitaxial layer. The epitaxial layer is usually in an atmosphere containing halogens, for example chlorine gas educated. The use of halogens, however, leads to destruction or roughening the surface of the epitaxial layer, making it difficult to smooth elements with To achieve surface on the substrate.
Darüber hinaus ist auch das Herstellungsverfahren der DSA-MOS-Tranastoren kompliziert. Beispielsweise wird auf einem Substrat eine Diffusion-Epitaxialschicht niedriger Verunreinigungskonzentration ausgebildet, deren Leitfähigkeitstyp dem des Substrats entgegengesetzt ist, auf der Spitaxialschicht wird in einer Tiefe bis zum Substrat eine erste Verunreinigungs-Diffusionsschicht ausgebildet, deren Leitfähigkeitstyp gleich dem des Substrats ist, in der Spitaxialschicht bzw. in der ersten Diffusionsschicht werden eine zweite und eine dritte Diffusionsschicht hoher Verunreiningskonzentration ausgebildet, deren Leitfähigkeitstyp dem des Substrats entgegengesetzt ist, die Drain-Elektrode wird an der zweiten Diffusionsschicht vorgesehen, die SourceElektrode an der dritten Diffusionsschicht und die Gate-Elektrode wird an der ersten Diffusionsschicht über einem Oxydfilm bestimmter Stärke angebracht. In addition, the manufacturing process of the DSA-MOS tranastors complicated. For example, a diffusion epitaxial layer is formed on a substrate low impurity concentration, the conductivity type of which corresponds to the of the substrate is opposite, on the spitaxial layer is at a depth a first impurity diffusion layer formed to the substrate, the Conductivity type the same as that of the substrate is, in the spitaxial layer or a second and a third diffusion layer are formed in the first diffusion layer high impurity concentration, the conductivity type of which is that of the substrate is opposite, the drain electrode is provided on the second diffusion layer, the source electrode on the third diffusion layer and the gate electrode attached to the first diffusion layer over a certain thickness of oxide film.
Bei DSA-MOS-Transistoren mit in der obigen Weise ausgebildeter Epitaxialschicht wirkt sich die rauhe Oberfläche der Epitaxialsehicht oder der im inneren Aufbau erzeugte Kristalldefekt auf die elektrischen Eigenschaften nachteilig aus und verringert die Genauigkeit der Herstellung. Es ist daher bisher nicht möglich, DSA-MOS-Transistoren herzustellen, die mit hohen Schaltungeschwindigkeiten arbeiten und billig herzustellen sind. For DSA-MOS transistors with the epitaxial layer formed in the above manner affects the rough surface of the epitaxial layer or the inside structure generated crystal defects adversely affect the electrical properties and decrease the accuracy of manufacture. It is therefore not yet possible to use DSA-MOS transistors that operate at high circuit speeds and are inexpensive to manufacture are.
Dervorliegenden Erfindung liegt daher die Aufgabe zugrunde, eine Halbleitervorrichtung zu schaffen, die in einem einfachen Herstellungsverfahren bei geringen Kosten hergestellt werden kann, ie glatte Oberflächen aufweist und bei hohen Schaltaeschwindig iten arbeitet. The present invention is therefore based on the object of a To provide semiconductor device that can be produced in a simple manufacturing process can be manufactured at low cost, ie has smooth surfaces and works at high gearshift speeds.
Der erfindungsgemäße DSA-MOS-Transitor zeichnet sich dadurch aus, daß er nur aus VerunreinigunOs-Diffusionsbeen ohne Verwendung einer Epitaxialschicht ausgebildet ist. The DSA-MOS transistor according to the invention is characterized by that it only consists of impurity diffusion layers without the use of an epitaxial layer is trained.
Anhand der in der beigefUgten Zeichnung dargestellten AusfUhrungsbeispiele wird die Erfindung im folgenden näher erläutert. Es zeigen: Fig. 1a und 1b eine Draufsicht bzw. einen Querschnitt längs der Linie Ib-Ib in Fig. la einer ersten Ausfuhrungsform der erfindungsgemäßen Halbleitervorrichtung; Fig. 2 einen Querschnitt zur Erläuterung der Arbeitsweise der erfindungsgemäßen Haibleit ervorrichtung; Fig. 3a bis 3d einzelne Arbeitsstufen des erfindungsgemäßen Verfahrens; Fig. 4 einen Teilschnitt einer zweiten Ausführungsform der erfindungsgemäßen Halbleitervorrichtung; und Fig. 5 einen Teilschnitt einer dritten Ausführungsform der erfindungsgemäßen Halbleitervorrichtung, angewandt an einem komplementären MOS-Transistor unter Verwendung eines herkömmlichen MOS-Transistors. On the basis of the exemplary embodiments shown in the attached drawing the invention is explained in more detail below. They show: FIGS. 1a and 1b Top view or a cross section along the line Ib-Ib in Fig. La a first Embodiment of the semiconductor device according to the invention; Fig. 2 is a cross section to explain the operation of the semiconductor device according to the invention; Fig. 3a to 3d individual work steps of the method according to the invention; Fig. 4 a Partial section of a second embodiment of the semiconductor device according to the invention; and FIG. 5 shows a partial section of a third embodiment of the invention Semiconductor device applied to a complementary MOS transistor using of a conventional MOS transistor.
Bei der Ausführungsform der Figuren la und 1b ist auf einem n-leitenden Halbleitersubstrat 1 ein rahmenförmiger, pleitender Diffusionsbereich 2 hoher Verunreinigungskonzentration (im folgenden kurz als erster Bereich bezeichnet) ausgebildet Ein Bereich 1b (im folgenden kurz als Inselbereich bezeichnet) ist wenigstens zum Teil vom Diffusionsbereich 2 seitlich umgeben. In the embodiment of Figures la and 1b is on an n-type Semiconductor substrate 1, a frame-shaped, p-conducting diffusion region 2 with a high impurity concentration (hereinafter referred to as the first area for short). An area 1b (in hereinafter referred to as the island region for short) is at least partly from the diffusion region 2 laterally surrounded.
Quer über den Inselbereich Ib ist ein p-leitender Diffusionsbereich 4 niedriger Verunreinigungskonzentration (2. Bereich) ausgebildet. In dem zweiten Bereich 4 ist ein n-leitender Bereich 5 (4. Bereich) ausgebildet, in den eine Verunreinigung mit hoher Konzentration eindiffundiert ißt. ueber einen Teil des ersten Bereichs 2 und einen Teil des lnselbereichs tb ist ein n-leitender Bereich 3 ausgebildet, in den eine Verunreinigung mit hoher Konzentration eindiffundiert ist (3.Bereich) Auf dem vierten, zweiten bzw. dritten Bereich sind in Form eines Metallüberzugs, beispielsweise aus Aluminium, eine Source-Elektrode S, eine Gate-Elektrode G und eine Drain-Elektrode D angebracht. Die Bereiche, die keine Elektrodenklemmen aufweisen, sind mit einer Isoliert schicht abgedeckt.Across the island area Ib is a p-type diffusion area 4 low impurity concentration (2nd area). In the second Area 4 is an n-conductive area 5 (4th area) in which an impurity with diffused in high concentration. over part of the first area 2 and An n-type region 3 is formed in part of the island region tb, in which an impurity with a high concentration has diffused (3rd area) on the fourth, second and third areas are in the form of a metal coating, for example made of aluminum, a source electrode S, a gate electrode G and a drain electrode D attached. The areas that do not have electrode clips are marked with a Isolated layer covered.
Bei dem DSA-MOS-Transistor des obigen Aufbaus sind das Substrat 1 unddie Drain (dritter Bereich 3) vom gleichen Iteitfähigkeitstyp und daher elektrisch rniteinander verbunden. Somit fließt beispielsweise ein Signalstrom von der Sourceklemme S nicht nur in den Drainbereich (dritter Bereich )),sondern auch in das Substrat 1. Hierdurch ist der Transistor im normalen Zustand nicht betriebsfähig bzw. durchschaltbar. Ferner kann ein DSA-StOS-Transistor- dieses Aufbaues bei integrierten Halbleiterschaltungen nicht verwendet werden, bei denen die Isolation zwischen den Elementen wesentlich ist. Um diese Schwierigkeit zu vermeiden, sind am ersten Diffusionsbereich 2 und am Halbleitersubstrat 1 Elektroden 7 bzw 7' angebracht und es wird zwischen diesen beiden Bereichen eine Vorspannung in Sperrichtung angelegt, so daß zwischen dem Drainbereich und dem Substrat 1 eine Verarmungsschicht erzeugt wird. Somit ist der Drainbereich vom Substrat 1 elektrisch isoliert. In the DSA-MOS transistor of the above structure, the substrate 1 is and the drains (third region 3) of the same conductivity type and therefore electrical connected to each other. Thus, for example, a signal current flows from the source terminal S not only into the drain region (third region), but also into the substrate 1. As a result, the transistor cannot be operated or switched through in its normal state. Furthermore, a DSA-StOS transistor of this structure can be used in integrated semiconductor circuits not used where the isolation between the elements is essential is. To avoid this difficulty, are on the first diffusion area 2 and on the semiconductor substrate 1 electrodes 7 or 7 'attached and it is between these two areas applied a bias in the reverse direction, so that between the Drain region and the substrate 1 a depletion layer is generated. So that is The drain region is electrically isolated from the substrate 1.
Wenn bei diesem DSA-MOS-Transistor während des Verfahrens zur Herstellung des n-leitenden Diffusionsbereiches 5 (vierter Bereich) hoher Verunreinigungskonzentration im p-leitenden Diffusionsbereich 4 (zweiter Bereich) niedriger V-erunreinigungskonzentration die SIaske zur Diffusion der Verunreinigung wenigstens in dem den Kanal bildenden Bereich unbeweglich gehalten wird, so ist es möglich, den Diffusionsbereich 4 (d. h. die Kanallänge) in einer Stärke von weniger als 1 P wie bei herkömmlichen DSB-MOS-Transistoren auszubilden. When in this DSA MOS transistor during the manufacturing process of the n-type diffusion region 5 (fourth region) of high impurity concentration in the p-type diffusion region 4 (second region) a low concentration of contaminants the mask for diffusion of the impurity at least in the one forming the channel Area is kept immobile, it is possible to use the diffusion area 4 (i.e. H. the channel length) with a thickness of less than 1 P as with conventional DSB-MOS transistors to train.
Fig. 2 zeigt einen Querschnitt zur Erlauterung des Prinzips des vorstehend beschriebenen DSA-MOS-Transistors, bei dem der Drainbereich 3 vom Substrat 1 elektrisch isoliert ist. In Fig. 2 ist angenommen, daß das Substrat 1 n-leit~end, der Diffusionsbereich 2 p-leitend und an die Klemmen 7 und 7' eine Gleichspannunsquelle 8 angeschlossen ist. Wird zwischen dem Substrat 1 und dem Diffusionsbereich 2 eine Vorspannung in Sperrrichtung angelegt, so breitet sich über den unschraffiert dart,estellten Bereich eine Verarmungsschicht 9 aus. Die Verarmung5-schicht, in der keine freien Elektronen vorhanden sind, entsteht nämlich in der I-Iahe des pn-Uberganges und breitet sich hauptsächlich in das Substrat 1 aus, dessen Verunreinigungskonzentration gering ist. Im Ergebnis dient daher die Verarmungsschicht 9 zur elektrischen Isolation zwischen dem Substrat 1 und dem die genannten Bereiche und Klemmen enthaltenden Element (Fig. 2). Zur Isolation des Inselbereichs 1b werden dessen Größe und die in Sperrichtung angelegte Vorspannung in geeigneter Weise gewählt. Fig. 2 shows a cross section to explain the principle of the above DSA-MOS transistor described, in which the drain region 3 from the substrate 1 electrically is isolated. In FIG. 2 it is assumed that the substrate 1 is n-conductive, the diffusion region 2 p-conducting and a DC voltage source 8 connected to terminals 7 and 7 ' is. If a bias voltage in Blocking direction applied, spreads over the unshaded dart, set area a depletion layer 9. The depletion 5-layer in which there are no free electrons are present, namely arises in the vicinity of the pn junction and spreads mainly in the substrate 1, the impurity concentration of which is low is. As a result, therefore, the depletion layer 9 serves for electrical insulation between the substrate 1 and that containing said areas and clamps Element (Fig. 2). To isolate the island area 1b, its size and the in Reverse direction applied bias selected in a suitable manner.
Die folgende Tabelle zeigt die Abhängigkeit der Ausbreitüngslänge von der Verunreinigungskonzentration des Substrats 1 bei drei auf einem n-leitenden Substrat ausgebildeten Verunreinigungs-Diffusionsschichten mit einer Tiefe von 1 /u, 2 /u bzw. The following table shows the dependency of the propagation length on the impurity concentration of the substrate 1 at three on one n-type Impurity diffusion layers formed on the substrate with a depth of 1 / u, 2 / u or
5µ, einer zwischen den Diffusionsschichten und dem Substrat angelegten Vorspannung in Sperrichtung von 5 Volt und einer Oberflächenkonzentration der p-leitenden Verunreinigungs-Diffusionsschicht von 1019 cm 3.5µ, one applied between the diffusion layers and the substrate Reverse bias of 5 volts and a surface concentration of the p-type Impurity diffusion layer of 1019 cm 3.
Tabelle
Fig. 4 zeigt den Querschnitt eines erfindungsremäßen bipolaren Seitentransistors der, mit der Ausnahme, daß die Elektrodenlage nach Ausbildung der Elektroden gemäß Fig 3d modifiziert ist, dem nach dem vorstehend beschriebenen erfindun'sgemäßen Verfahren hereestellte Transistor ähnelt. Hierbei werden der Diffusionsbereich 3 hoher Verunreinigungskonzentration als Kollektorbereich C, der Diffusionabereich 5 hoher Verunreinigungskonzentration als Emitterbereich E und der Diffusionsbereich 4 als Basisbereich B verwendet. Hält man, wie allgemein bei integrierten Halbleiterschaltungen, das Substrat auf einem höheren Potential als jeden Diffusionsbereich, so entsteht zwischen dem Element und dem Substrat, wie in Fig. 2 dargestellt, eine Verarmungsschicht. Somit entsteht zwischen dem Substrat 1 und dem Diffusionsbereich 2 eine Sperr-Vorspannung. Damit ist es möglich, ohne eine Sperr-Vorspannungs-Einrichtung vorzusehen, den Kollektor a und das Substrat 1 durch die Ausbreitung der Verarmungsschicht wie bei dem DSA-MOS-Transistor voneinander zu isolieren und somit den Transistor auf normale Weise zu betreiben. Beträgt beispielsweise die Spannung des Substrats 10 Volt und das an die Basis B angelegte Signal maximal 2 Volt, so beträgt die Sperr-Vorspannung 8 Volt. In diesem Zustand ist die Verarmungsschicht voll ausgebreitet und isoliert das Element vom Substrat. 4 shows the cross section of a bipolar side transistor according to the invention the, with the exception that the electrode layer according to the formation of the electrodes Fig. 3d is modified, according to the inventive concept described above The procedure here is similar to the transistor. The diffusion area 3 high impurity concentration as collector area C, the diffusion area 5 high impurity concentration as the emitter area E and the diffusion area 4 used as base area B. If, as is generally the case with integrated semiconductor circuits, the substrate at a higher potential than any diffusion region, so arises between the element and the substrate, as shown in Fig. 2, a depletion layer. A reverse bias voltage thus arises between the substrate 1 and the diffusion region 2. It is thus possible, without providing a reverse bias device, the collector a and the substrate 1 by the depletion layer spread like the DSA-MOS transistor isolate from each other and thus operate the transistor in the normal manner. For example, if the voltage of the substrate is 10 volts and that to the base B. applied signal is a maximum of 2 volts, the reverse bias voltage is 8 volts. In this State, the depletion layer is fully expanded and isolates the element from Substrate.
Fig. 5 zeigt einen erfindungsgmäBen Kompleme ntär-MOS-Transistor, der im Aufbau dem Transistor der Fig. 2 ähnelt. Der durch strichpunhtierte Linien eingerahmte Bereich 30 enthalt ein Halbleitersubstrat 1, einen rahmen- oder ringförinigen pZ leitenden Diffusionebereich 2 hoher Verunreinigungskonzentration, der auf dem Substrat 1 ausgebildet ist, einen über einen Teil des Diffusionsbereichs 2 und einen Teil des vom Diffusionsbereich 2 umgebenen Bereichs Ib ausgebildeten p-leitenden Diffusionsbereich 4 niedriger Verunreindigungskonzentration, einen in einem Teil des Inselbereichs 1b und dem anderen Teil des Diffusionsbereichs 2 ausgebildeten n-leitenden Difiusionsbereich 3 hoher Konzentration für die Drain D, einen im Diffusionsbereich 4 ausgebildeten nleitenden Diffusionsbereich 5 hoher Verunreinigungskonzentration für die Source S, eine auf der Oberfläche des Elements ausgebildete Isolierschicht 6 und an bestimmten Bereichen vorgesehene Elektroden 7. 5 shows a complementary MOS transistor according to the invention, which is similar in structure to the transistor of FIG. The one by dashed lines The framed area 30 contains a semiconductor substrate 1, a frame-shaped or ring-shaped one pZ conductive diffusion area 2 high impurity concentration on the Substrate 1 is formed, one over a part of the diffusion region 2 and one Part of the area Ib surrounded by the diffusion area 2 formed p-conductive Diffusion region 4 of low impurity concentration, one in one part of the island region 1b and the other part of the diffusion region 2 are formed n-type diffusion area 3 high concentration for the drain D, one in the diffusion area 4 formed conductive diffusion region 5 high impurity concentration for the source S, an insulating layer formed on the surface of the element 6 and electrodes 7 provided in certain areas.
Bei diesem MOS-Transistor 30 haben das Substrat 1 und die Drain D den gleichen Leitfähigkeitstyp und sind daher elektrisch miteinander verbunden. LeOt man zwischen dem Diffusionsbereich 2 und dem Halbleitersubstrat 1 eine Sperr-Vorspannung an, so entsteht zwischen der Drain D und dem Substrat 1 eine Verarmungsschicht, so daß die Drain D vom Substrat t elektrisch isoliert wird Darauf werden in einem Abstand von dem MOS-Transistor 30 auf dem Substrat 1 p-leitende Verunreinigungs-Diffusionsbereiche 2a und 2b für die Source S und die Drain D ausgebildet. In this MOS transistor 30, the substrate 1 and the drain D have have the same conductivity type and are therefore electrically connected to each other. LeOt is a reverse bias voltage between the diffusion region 2 and the semiconductor substrate 1 on, a depletion layer is created between the drain D and the substrate 1, so that the drain D is electrically isolated from the substrate t Distance from the MOS transistor 30 on the substrate 1 p-type impurity diffusion regions 2a and 2b for the source S and the drain D are formed.
Uber einem Isolierfilm 6 wird auf dem Substrat 1 in dem Bereich zwischen der Source und der Drain eine Gateklemme G angebracht.Over an insulating film 6 is on the substrate 1 in the area between a gate terminal G is attached to the source and drain.
Hierdurch entsteht ein MOS-Transistor 40 mit einem Kanal des entgegengesetzten Leitfähigkeitstyps.This creates a MOS transistor 40 with one channel of the opposite Conductivity type.
Auf diese Weise wird durch die NOS-Transistoren 30 und 40 ein Komplementär-MOS-Transistor gebildet. Wird an die einzelnen Gateklemmen G der MOS-Transistoren eine geeignete Sannung angelegt, so schalten diese und es fließt ein Strom von der Drai D zur Source S in MOS-Transistor 30 und von der Drain D zur Source S im MOS-Transistor 40. Unter dieser Bedingung wird durch die zwischen dem Diffusionsbereich 2 und dem Substrat 1 des MOS-Transistors 30 anliegende Sperr-Vorspannung nur in dem den MOS-Transistor 30 umgebenden Bereich eine Verarmungsschicht ausgebildet. Hierdurch wird der MOS-Transistor 30 sowohl gegenüber dem MOS-Transistor 40 als auch dem Substrat 1 elektrisch isoliert und der Drainstrom es MOS-Transistor 30 fließt nicht in die Seite des Substrats 1, so daß der Transistor normal betrieben wird. In this way, the NOS transistors 30 and 40 become a complementary MOS transistor educated. If a suitable one is applied to the individual gate terminals G of the MOS transistors When voltage is applied, they switch and a current flows from Drai D to the source S in MOS transistor 30 and from drain D to source S in MOS transistor 40. Sub this condition is established by the between the diffusion region 2 and the substrate 1 of the MOS transistor 30 applied reverse bias only in the MOS transistor 30 surrounding area formed a depletion layer. This will make the MOS transistor 30 electrically isolated from both the MOS transistor 40 and the substrate 1 and the drain current of the MOS transistor 30 does not flow into the side of the substrate 1 so that the transistor operates normally.
Wie oben beschrieben, enthält der erfindungsgemäße Komplementär-MOS-Transistor nur die Verunreinigungs-Diffusionsbereiche 2, 3, 4, 5, 2a und 2b. Die Diffusionsbereiche 2a und 2b des MOS-Transistors 40 werden gleichzeitig mit dem Diffusionsbereich 2 des MOS-Transistors 30 ausgebildet, so daß ein eigenes Verfahren zur Herstellung des MOS-Transistors 40 eingespart wird. Ferner erübrigt sich gemäß der Erfindung ein zusätzlicher Diffusionsbereich des gegenüber dem des Substrats entgegengesetzten Leitfähigkeitstyps, der einen der beiden MOS-Transistoren enthalten mußte. As described above, the complementary MOS transistor of the present invention includes only the impurity diffusion regions 2, 3, 4, 5, 2a and 2b. The diffusion areas 2a and 2b of the MOS transistor 40 become simultaneously with the diffusion region 2 of the MOS transistor 30 formed so that a proprietary method of manufacturing of the MOS transistor 40 is saved. Further unnecessary according to According to the invention, an additional diffusion area of the compared to that of the substrate opposite conductivity type, which contain one of the two MOS transistors had to.
Somit kann der Platzbedarf der beiden Elemente verringert und dic Integrationsdichte beträchtlich erhöht werden. Gemäß der Erfindung wird der Kanal im MOS-Transistor 30 nach dem sogenannten Doppeldiffusionsverfahren hergestellt, so daß die Kanallänge und damit der Trägerxfeg vom Gate zur Source beträchtlich verringert werden kann. Mit anderen Worten, bei dem erfindungsgemäßen Komplementär-MOS-Transistor ist die Schaltgeschwindigkeit wesentlich höher als bei herkömmlichen Transistoren dieser Art.Thus, the space requirement of the two elements can be reduced and dic Integration density can be increased considerably. According to the invention, the channel manufactured in the MOS transistor 30 according to the so-called double diffusion process, so that the channel length and thus the carrier xfeg from gate to source is considerable can be reduced. In other words, in the complementary MOS transistor according to the invention the switching speed is much higher than with conventional transistors this kind.
Bei dem DSS IOS Transistor und dem bipolaren Seitentransistor wird ein n-leitendes Substrat verwendet. Statt des n-leitenden Substrats kann jedoch auch ein p-leitendes Substrat verwendet werden. Dabei müssen auch die Leitfähigkeiten der Bereiche auf dem Substrat von p nach n und n nach p umgekehrt werden. Es ist nicht immer notwendig, daß der Diff,usionsbereich 2 den Inselbereich 1b durchgehend umgibt. Statt des Diffusionsbereiches 2 können auch mehrere voneinander durch die Ausbreitung der Verarmungeschicht isolierte Diffusionebereiche hergestellt werden, wobei zwischen den einzelnen Diffusionsbereichen eine Sperr-Vorspannung aet wird. Hierdurch ergibt sich der gleiche Effekt wie beim Diffusionsbereich 2. With the DSS IOS transistor and the bipolar side transistor an n-type substrate is used. Instead of the n-type substrate, however, a p-type substrate can also be used. The conductivities must also be there of the areas on the substrate are reversed from p to n and n to p. It is it is not always necessary for the diffusion area 2 to go through the island area 1b surrounds. Instead of the diffusion region 2, several of one another can also pass through the Propagation of the depletion layer, isolated diffusion regions are produced, a reverse bias voltage is aet between the individual diffusion areas. This results in the same effect as in the case of diffusion region 2.
Bei den vorstehend beschriebenen Ausführungsformen werden die verschieden leitfähigen Bereiche durch Verunreinigungsdiffusion in einer auf hoher Temperatur gehaltenen Atmosphäre hergestellt. Natürlich können die Bereiche auch durch Ionen-Implantation hergestellt werden. In the above-described embodiments, they become different conductive areas due to impurity diffusion in a high temperature maintained atmosphere. Of course, the areas can also be implanted by ions getting produced.
Durch die Erfindung ist es möglich, seibstausgerichtete MOS-Transistoren nur durch Verunreinigungsdiffusion herzustellen, ohne daß man auf eine Epitaxialsehicht angewiesen wäre. Hierdurch erhält die erfindungsgemäße Halbleitervorrichtung günstige elektrische Eigenschaften, beispielsweise arbeitet sie bei hoher Schaltgeschwindigkeit. Ferner ermöglicht die Erfindung eine leichte Ausbildung verschiedener Schaltungselemente, beispielsweise eines bipolaren Seitentransistors, auf einem gemeinsamen Substrat. Die Erfindung bietet also beträchtliche Vorteile, sowohl hinsichtlich der Herstellung als auch hinsichtlich der Anwendung. The invention makes it possible to use self-aligned MOS transistors produced only by impurity diffusion without affecting an epitaxial layer would be instructed. This gives the semiconductor device according to the invention favorable electrical properties, for example, it works at high switching speeds. Furthermore, the invention enables easy design of various circuit elements, for example a bipolar side transistor, on a common substrate. The invention thus offers considerable advantages, both in terms of manufacture as well as in terms of application.
Patentans pruchePatent claims
Claims (3)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP45064302A JPS4916236B1 (en) | 1970-07-24 | 1970-07-24 |
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DE2136509A1 true DE2136509A1 (en) | 1972-11-23 |
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DE19712136509 Pending DE2136509A1 (en) | 1970-07-24 | 1971-07-21 | Semiconductor device |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2349958A1 (en) * | 1976-04-29 | 1977-11-25 | Sony Corp | FIELD EFFECT TRANSISTOR WITH ONE INSULATED TRIGGER |
FR2458907A1 (en) * | 1979-06-12 | 1981-01-02 | Thomson Csf | Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor |
US4376286A (en) * | 1978-10-13 | 1983-03-08 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US4705759A (en) * | 1978-10-13 | 1987-11-10 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US4809047A (en) * | 1983-09-06 | 1989-02-28 | General Electric Company | Insulated-gate semiconductor device with improved base-to-source electrode short and method of fabricating said short |
US4959699A (en) * | 1978-10-13 | 1990-09-25 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US5869371A (en) * | 1995-06-07 | 1999-02-09 | Stmicroelectronics, Inc. | Structure and process for reducing the on-resistance of mos-gated power devices |
-
1970
- 1970-07-24 JP JP45064302A patent/JPS4916236B1/ja active Pending
-
1971
- 1971-07-21 DE DE19712136509 patent/DE2136509A1/en active Pending
- 1971-07-23 NL NL7110163A patent/NL7110163A/xx unknown
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2349958A1 (en) * | 1976-04-29 | 1977-11-25 | Sony Corp | FIELD EFFECT TRANSISTOR WITH ONE INSULATED TRIGGER |
US4376286A (en) * | 1978-10-13 | 1983-03-08 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US4705759A (en) * | 1978-10-13 | 1987-11-10 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US4959699A (en) * | 1978-10-13 | 1990-09-25 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US5191396A (en) * | 1978-10-13 | 1993-03-02 | International Rectifier Corp. | High power mosfet with low on-resistance and high breakdown voltage |
US5338961A (en) * | 1978-10-13 | 1994-08-16 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US5598018A (en) * | 1978-10-13 | 1997-01-28 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
US5742087A (en) * | 1978-10-13 | 1998-04-21 | International Rectifier Corporation | High power MOSFET with low on-resistance and high breakdown voltage |
FR2458907A1 (en) * | 1979-06-12 | 1981-01-02 | Thomson Csf | Field effect transistor with adjustable pinch off voltage - has doping chosen in intermediate layer to reduce effect of parasitic bipolar transistor |
US4809047A (en) * | 1983-09-06 | 1989-02-28 | General Electric Company | Insulated-gate semiconductor device with improved base-to-source electrode short and method of fabricating said short |
US5869371A (en) * | 1995-06-07 | 1999-02-09 | Stmicroelectronics, Inc. | Structure and process for reducing the on-resistance of mos-gated power devices |
US6046473A (en) * | 1995-06-07 | 2000-04-04 | Stmicroelectronics, Inc. | Structure and process for reducing the on-resistance of MOS-gated power devices |
Also Published As
Publication number | Publication date |
---|---|
JPS4916236B1 (en) | 1974-04-20 |
NL7110163A (en) | 1972-01-26 |
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