DE2006703A1 - Insulation layer on a semiconductor base body - Google Patents

Insulation layer on a semiconductor base body

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Publication number
DE2006703A1
DE2006703A1 DE19702006703 DE2006703A DE2006703A1 DE 2006703 A1 DE2006703 A1 DE 2006703A1 DE 19702006703 DE19702006703 DE 19702006703 DE 2006703 A DE2006703 A DE 2006703A DE 2006703 A1 DE2006703 A1 DE 2006703A1
Authority
DE
Germany
Prior art keywords
layer
titanium
base body
semiconductor base
titanium oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19702006703
Other languages
German (de)
Inventor
Dietrich Dipl Phys Limann Dirk 8000 München Widmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19702006703 priority Critical patent/DE2006703A1/en
Priority to CH170671A priority patent/CH522960A/en
Priority to AT102271A priority patent/AT327291B/en
Priority to FR7104399A priority patent/FR2079406B1/fr
Priority to NL7101934A priority patent/NL7101934A/xx
Priority to CA105,339A priority patent/CA970257A/en
Priority to SE01919/71A priority patent/SE365900B/xx
Priority to GB2166171A priority patent/GB1312183A/en
Publication of DE2006703A1 publication Critical patent/DE2006703A1/en
Pending legal-status Critical Current

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

auf_einem_Halbleiter^rundkör^eron_a_semiconductor ^ round body

Die Erfindung betrifft eine Halbleiteranordnung, insbesondere integrierte Halbleiter-Schaltungsanordnung mit wenigstens einer Isolationsschicht auf dem Halbleitergrundkörper, und ein Verfahren zur Herstellung dieser Isolationsschicht.The invention relates to a semiconductor arrangement, in particular an integrated semiconductor circuit arrangement having at least one Insulation layer on the semiconductor base body, and a method for producing this insulation layer.

Die allgemein bei Halbleiterbauelementen und integrierten Schaltungen verwendeten Isolationsschichten bestehen aus Siliciumdioxid. Dieses wird durch Oxidation der Oberfläche des Halbleiterkörpers aus Silicium in einem sauerstoffhaltigen Medium erzeugt.Those in general for semiconductor components and integrated circuits The insulation layers used consist of silicon dioxide. This is caused by oxidation of the surface of the semiconductor body produced from silicon in an oxygen-containing medium.

Ein bekanntes Verfahren zur Herstellung einer Isolationsschicht aus Siliciumdioxid geht von einem mit verschiedenen pn-Übergängen versehenen Halbleiterkörper aus. Auf die Oberfläche dieses Halbleiterkörpers wird zunächst Siliciumdioxid aufgebracht. Entsprechend den gewünschten Kontakten zu den einzelnen pn-Übergängen werden in diese Isolatorschicht mit Hilfe der Fototechnik Löcher geätzt. Daran anschließend wird die Oberfläche der verbliebenen Siliciumdioxidschicht und des durch die Löcher freigelegten Halbleiterkörpers mit einer dünnen Titanschicht bedampft. Auf die Titanschicht wird ganzflächig eine Goldschicht aufgedampft. Die Titanschicht wirkt dabei als Haftschicht für die Goldschicht. Durch eine v/eitere J?ototechnik wird die Goldschicht entsprechend den herzustellenden Strukturen weggeätzt. Insbesondere wird die Goldschicht außerhalb der Kontaktflecken und der Leitbahnen zwischen den einzelnen Bauelementen entfernt. In einem weiteren Arbeitsgang wird schließlich noch die durch die Goldätzung freigelegte Titanschicht abgeätzt, um unerwünschte elektrische Kurzschlüsse zu vermeiden.A known method for producing an insulation layer from silicon dioxide is based on a semiconductor body provided with various pn junctions. First of all, silicon dioxide is applied to the surface of this semiconductor body. According to the desired contacts to the individual pn junctions, holes are etched into this insulator layer with the help of photo technology. Then the surface of the remaining silicon dioxide layer and the semiconductor body exposed through the holes are vapor-deposited with a thin titanium layer. A gold layer is vapor-deposited over the entire surface of the titanium layer. The titanium layer acts as an adhesive layer for the gold layer. The gold layer is etched away according to the structures to be produced using a further jetting technique. In particular, the gold layer is removed outside the contact pads and the interconnects between the individual components. In a further operation, the titanium layer exposed by the gold etching is finally etched off in order to avoid undesired electrical short circuits.

VPA 9/110/0018VPA 9/110/0018

Q9835/1379Q9835 / 1379

Dieses bekannte Verfahren ist in seiner Durchführung aufwendig, da es viele einzelne Arbeitsgänge aufweist. Weiterhin weisen die nach diesem Verfahren hergestellten Kontaktflecken und Leitbahnen an ihren Rändern hohe Stufen auf, die in der Größenordnung yon etwa 0,8 /um liegen. Derartige Stufen sind aber vor allem in der Mikrotechnik unerwünscht, und bei Leitbahnüberiireuzungen technologisch schwer zu beherrschen.This known method is complex to carry out because it has many individual operations. Furthermore, the contact pads and interconnects produced by this method have high steps at their edges, which are in the order of magnitude of approximately 0.8 μm. Such stages are undesirable, especially in microtechnology, and technologically difficult to control in the case of interconnecting pathways.

Es ist Aufgabe der vorliegenden Erfindung, eine einfach herstellbare Isolatorschicht anzugeben, die zudem die oben geschilderw.on Nachteile hoher Stufen an den Rändern der Leitbahnstrukturen vermeidet.It is the object of the present invention to provide an easy-to-manufacture Specify the insulating layer, which also has the above Schildw.on Avoids disadvantages of high steps at the edges of the interconnect structures.

Diese Aufgabe wird erfindungsgemäß dadurch gelöst, daß die Isolatorschicht eine Titanoxidschicht ist.According to the invention, this object is achieved in that the insulator layer is a titanium oxide layer.

Eine Weiterbildung der Erfindung besteht in einem Verfahren zur Herstellung der Titanschicht.A further development of the invention consists in a method for producing the titanium layer.

Es wird nämlich vorgeschlagen, auf einen Halbleitergrundkörper zunächst eine Titanschicht aufzubringen und diese Titanschicht dann zu einer Titanoxidschicht zu oxidieren. Vorzugsweise weist die Titanschicht eine Dicke von etwa 0,5 /um auf.This is because it is proposed to first apply a titanium layer and this titanium layer to a semiconductor base body then oxidize to a titanium oxide layer. The titanium layer preferably has a thickness of approximately 0.5 μm.

Eine 'Weiterbildung der Erfindung besteht darin, daß die Titanschicht in WasserstoffSuperoxid bei etwa 107 0C während etwa 10 Minuten zu der Titanoxidschicht oxidiert wird. Diese Oxidation kann beispielsweise aber auch in einer Salpetersäure-Atmosphäre durchgeführt werden.A further development of the invention is that the titanium layer is oxidized in hydrogen superoxide at about 107 ° C. for about 10 minutes to form the titanium oxide layer. This oxidation can, for example, also be carried out in a nitric acid atmosphere.

Zum bereichsweisen Aufbringen der Isolationsschicht auf den Halbleitergrundkörper entsprechend den gewünschten Kontakten und Leitbahnstrukturen werden in vorteilhafter Weise schließlich noch folgende Verfahrensschritte vorgeschlagen:For applying the insulation layer in regions to the semiconductor base body in accordance with the desired contacts and interconnect structures, the following procedural steps are finally proposed in an advantageous manner:

a) Aufbringen der Titanschicht auf den Halbleitergrundkörper,a) application of the titanium layer to the semiconductor base body,

b) Aufbringen einer Goldschicht auf die Titanschicht,b) applying a gold layer to the titanium layer,

c) Entfernen der Goldschicht entsprechend der gewünschten Struktur mittels Fototechnik,c) Removal of the gold layer according to the desired structure using photo technology,

109835/1379109835/1379

VPA 9/110/0018 - 3 -VPA 9/110/0018 - 3 -

d) Oxidieren der dadurch freigelegten Bereiche der Titanschicht zu der Titanoxidschicht.d) Oxidizing the areas of the titanium layer exposed thereby to form the titanium oxide layer.

Lurch dieses Yerfaliren v/ird ermöglicht, das eingangs erwähnte bekannte Vorfahren sur Herstellung einer Isolationsschicht auf einen llalbleitergrundkürper wesentlich abzukürzen. Sin v/eiterer Vorteil dieses erfindungsgeiaäßen Verfahrens besteht darin, daß die an den Rändern der Leitbahnen auftretenden Stufen lediglich eine Hohe von etwa 0,1 /um aufweisen, und daher für die Mikrotechnik besonders geeignet sind. Dies trifft vor allem auch dann zu, wenn ÜberkreuKimgen" von Leitbahnen durchgeführt v/erden müssen.This failure makes it possible to substantially shorten the aforementioned known method of producing an insulating layer on a basic semiconductor body. Another advantage of this method according to the invention is that the steps occurring at the edges of the interconnects have a height of only about 0.1 μm and are therefore particularly suitable for microtechnology. This is especially true when overcrossing kimgen "must be carried out by interconnects.

Zur Leitbahnüberkreuzung, d. h., sur Ausbildung einer weiteren Leitbahnebene auf einem mit einer Leitbahnebene versehenen Halbleitergrundkcrper wird in einer Weiterbildung der Erfindung noch vorgeschlagen, daß als Isolationsschicht zwischen den Leitbahnebenen eine Titanoxidschicht verwendet v/ird, und daß sur elektrischen Verbindung zwischen Kontakten der einen Xeitbahnebene und der weiteren Leitbahnebene eine Titanschicht verwendet wird. In vorteilhafter V/eise v/ird die Titanoxidschicht dabei durch bereichsv/eise Oxidation der l'itanschiclit gebildet.To cross the track, d. h., sur training another Interconnect level on a semiconductor base body provided with an interconnect level is provided in a further development of the invention It is also proposed that a titanium oxide layer be used as the insulation layer between the interconnect levels, and that sur electrical connection between contacts of the one channel plane and a titanium layer is used for the further interconnect level. The titanium oxide layer is advantageously used thereby formed by partial oxidation of l'itanschiclite.

V/eitere Merkmale und Einzelheiten der Erfindung ergeben sich aus der nachfolgenden Beschreibung von Ausführungsbeispielen anhand der Figuren.Further features and details of the invention result from the following description of exemplary embodiments with reference to the figures.

Us zeigen:Us show:

Figur 1: Den erfindungsgemäßen Gegenstand in zwei Ausführ ungs formen ;Figure 1: The object according to the invention in two versions ungs forms;

Figur 2 bis 4: Schnitte durch ein Ausfiüirimgsbeispiel der Erfindung ;FIG. 2 to 4: Sections through an exemplary embodiment of the invention ;

Figur 5 bis 6: Schnitte durch ein weiteres AusführungsbeispielFigure 5 to 6: Sections through a further embodiment

der Erfindung.the invention.

VPA 9/110/0018 109835/1379 "4" VPA 9/110/0018 109835/1379 " 4 "

BAO ORIGINALBAO ORIGINAL

In der durch eine strichpunktierte Linie abgetrennten linken Hälfte der Figur 1 ist auf einem Halbleitergrundkörper 1 eine Titanschicht 2 und eine Titanoxidschicht 3 vorgesehen. Wie in der rechten Hälfte in der Figur 1 gezeigt ist, können die Titanschicht 2 und die Titanoxidschicht 3 auch auf einer Siliciumdioxidschicht 10 angeordnet sein.In the left half of FIG. 1 separated by a dash-dotted line, there is a semiconductor base body 1 Titanium layer 2 and a titanium oxide layer 3 are provided. As shown in the right half in Figure 1, the titanium layer 2 and the titanium oxide layer 3 can also be arranged on a silicon dioxide layer 10.

Das Verfahren zur Herstellung des Gegenstandes der Figur 1 besteht darin, daß auf den Halbleitergrundkörper 1 beziehungsweise auf die Siliciumdioxidschicht 10 zunächst ganzflächig eine Titanschicht 2 aufgebracht wird. Die Titanschicht 2 v/eist dabei eine Dicke von etwa 0,5 /um auf. Vorzugsweise wird die Titanschicht aufgedampft. Soll die Titanschicht 2 nicht ganzflächig sein, sondern zu bestimmten Stellen des Halbleitergrundkörpers 1 Fenster enthalten, so wird nach der Titan-Aufdampfung das Titan an diesen Stellen mit Hilfe der üblichen fotolithografischen Technik weggeätzt. Die Umwandlung der Titanschicht 2 an bestimmten Bereichen in die Titanoxidschicht erfolgt bevorzugt durch etwa 10 Minuten langes Erwärmen in V/asserstoffSuperoxid bei etwa 107 0C oder in Salpetersäure oder in einem anderen oxidierenden Medium. Auch in einer Sauerstoff enthaltenden Atmosphäre bei 400 bis 500 0C ist eine Oxidation der Titanschicht zu der Titanoxidschicht möglich.The method for producing the object of FIG. 1 consists in first applying a titanium layer 2 over the entire surface of the semiconductor base body 1 or the silicon dioxide layer 10. The titanium layer 2 has a thickness of approximately 0.5 μm. The titanium layer is preferably vapor deposited. If the titanium layer 2 is not intended to be over the entire surface, but rather to contain windows at certain points on the semiconductor base body 1, after the titanium vapor deposition, the titanium is etched away at these points with the aid of the customary photolithographic technique. The conversion of the titanium layer 2 in certain areas takes place in the titanium oxide layer preferably about 10 minutes long heating in V / asserstoffSuperoxid at about 107 0 C or in nitric acid or in other oxidizing medium. Oxidation of the titanium layer to form the titanium oxide layer is also possible in an oxygen-containing atmosphere at 400 to 500 ° C.

In den Figuren 2 bis 6 werden sich entsprechende Teile mit den gleichen Bezugszeichen versehen wie in der Figur 1.In FIGS. 2 to 6, corresponding parts are provided with the same reference numerals as in FIG. 1.

In der Figur 2 ist auf der Siliciumdioxidschicht 10 eine Aluminiumleitbahn 11 und ein Aluminiurnkontaktfleck 12 vorgesehen. Auf den Gegenstand der Figur 2 wird, wie in der Figur 3 dargestellt, zunächst eine etwa 0,3 /um dicke Titanschicht 2 und darauf schließlich eine Goldschicht 15 aufgedampft. Dann' wird In FIG. 2, an aluminum interconnect 11 and an aluminum contact pad 12 are provided on the silicon dioxide layer 10. , As shown in Figure 3 to the subject of Figure 2, initially about 0.3 / eventually evaporated to a thick titanium layer 2 and then a gold layer 15 °. Then ' will

" die Goldschicht i5 mit Hilfe der üblichen fotolithografischen Technik überall, mit Ausnahme der Kontaktflecken, abgeätzt. Schließlich wird die Titanschicht 2 dort, wo sie nach dem Ab ätzen der Goldschicht 15 frei lie^t, wie in der Figur 4 darge- " the gold layer 15 is etched away everywhere with the help of the usual photolithographic technique, with the exception of the contact pads. Finally , the titanium layer 2 is where it is exposed after the etching of the gold layer 15, as shown in FIG.

. stellt, zu der Titanoxidschicht 3 oxidiert. Die verblioftcne . is oxidized to the titanium oxide layer 3. The astonished

VPA 9/110/0018 109835/1379 -5- VPA 9/110/0018 109835/1379 -5-

2Ü067032Ü06703

Goldschicht 15 v/ird mit einem Golddraht kontaktiert oder, wie in der Figur 4 dargestellt, galvanisch zu einer podestartigen Erhöhung 25 verstärkt, so daß elektrische Anschlüsse leichter hergestellt werden können.Gold layer 15 is contacted with a gold wire or how shown in FIG. 4, galvanically reinforced to form a pedestal-like elevation 25, so that electrical connections are easier can be produced.

Statt der Goldschicht 15 kann in vorteilhafter Weise auch eine Aluminiumschicht verwendet werden. Die Aluminiumschicht wird v/ie die Goldschicht gansflächig auf die Titanschicht 2 aufgebracht. Dann wird die Aluminiumschicht selektiv so geätzt, daß sie nur noch an den gewünschten Stellen stehen "bleibt. Die freiliegende Titanschieht wird zu einer Titanoxidschicht oxidiert, während die unter der verbliebenen Aluminiumschicht liegende Titanschieht nicht verändert wird.Instead of the gold layer 15, an aluminum layer can also be used in an advantageous manner. The aluminum layer will v / ie the gold layer is applied over the entire surface of the titanium layer 2. Then the aluminum layer is selectively etched so that it only remains in the desired places ". The exposed titanium layer is oxidized to a titanium oxide layer, while the titanium layer under the remaining aluminum layer is not changed.

Bin weiterer Vorteil des erfindungsgemäßen Verfahrens besteht darin, daß die Titanoxidschicht 3 in Phosphorsäure wieder abgelöst werden kann, ohne daß das gegebenenfalls darunterliegende Siliciumdioxid angegriffen wird. Schließlich ist es auch noch vorteilhaft, daß das in den Figuren 2 bis 4 beschriebene erfindungsgemäße Verfahren bei, im Vergleich zur thermischen Oxidation, niedrigen Temperaturen durchgeführt v/erden kann.There is a further advantage of the method according to the invention in that the titanium oxide layer 3 is detached again in phosphoric acid can be without attacking any underlying silicon dioxide. After all, it is too still advantageous that the method according to the invention described in FIGS. 2 to 4, in comparison to the thermal Oxidation, carried out at low temperatures, can be grounded.

In den Figuren 5 und 6 ist ein Ausführungsbeispiel zur Leitbahnüberkreuzung dargestellt. Zunächst wird auf den Halbleitergrundkörper 1 eine Titanschicht 2, die beispielsweise 0,8 /um dick sein soll und auf diese eine Aluminiumschicht 26, die beispielsweise 0,1 /um dick ist, aufgedampft. Dann wird die Aluminiumschicht 26, wie in der Figur 5 dargestellt, selektiv mit Hilfe der üblichen fotolithografischen Technik geätzt, so daß das Leitbahnsystem einer ersten Leitbahnebene stehen bleibt. Daraufhin werden üie nicht von Aluminium bedeckten Flächen der Titanschieht 2 in einem geeigneten oxidierenden Medium zu der Titanoxidschicht 3 oxidiert.In FIGS. 5 and 6, there is an exemplary embodiment for interconnecting interconnects shown. First, a titanium layer 2, for example 0.8 / μm should be thick and on this an aluminum layer 26, for example 0.1 / µm thick, is vapor-deposited. Then the Aluminum layer 26, as shown in FIG. 5, selectively etched with the aid of the usual photolithographic technique, see above that the interconnect system of a first interconnect level remains. Thereupon the surfaces of the titanium sheet 2 not covered by aluminum are placed in a suitable oxidizing medium Titanium oxide layer 3 is oxidized.

Auf den Gegenstand der Figur 5 v/ird dann eine weitere Titanachicht ,>' : wie oben beschrieben, aufgebracht. Dann v/erden lediglich die Kontaktstellen zwischen der ersten und zweiten Leitbahnebene nicht zu der Titanoxidschicht 30 oxidiert, so A further titanium layer is then applied to the object of FIG. 5, as described above. Then only the contact points between the first and second interconnect planes are not oxidized to form the titanium oxide layer 30, see above

109835/1379109835/1379

VPA 9/110/0018 - 6 -VPA 9/110/0018 - 6 -

" 6 " 2U06703" 6 " 2U06703

daß die in der Figur 6 dargestellte 'iiumjcl.ichu ^O zurL'ul·.-bleibt. Auf der Titanoxidschicht 30 wird schließlich eine weitere Titanschicht 32 aufgebracht, die entsprechend der zweiten gewünschten Leitbahnstruktur, welche auf dieselbe Weise wie die erste Leitbahnstruktur entsteht, zu der Titanoxidschicht 35 oxidiert wird.that the 'iiumjcl.ichu ^ O shown in Figure 6 remains forL'ul ·.-. Finally, a further titanium layer 32 is applied to the titanium oxide layer 30, which corresponds to the second desired interconnect structure, which is produced in the same way as the first interconnect structure, to the titanium oxide layer 35 is oxidized.

Die dabei an den Leitbahnrändern entstehenden Stufen sind nur etwa 0,1 /um hoch, während die bei bekannten Verfahren entstehenden Stufen 0,8 /um hoch sind.The steps that arise at the edges of the interconnect are only about 0.1 / µm high, while those resulting from known processes Steps are 0.8 / µm high.

9 Patentansprüche 6 Figuren9 claims 6 figures

VPA ij/110/0018 109835/1379VPA ij / 110/0018 109835/1379

BAD ORIGINALBATH ORIGINAL

Claims (1)

e n t a nsprü chee nt a ngs f !./Halbleiteranordnung, insbesondere integrierte Halbleiter-Schaltungsanordnung mit wenigstens einer Isolations 3 chich/fc auf dem Halbleitergrundkörper, dadurch g e 3:ennzeichnet , daß die Isolationsschicht eine Titanoxidschicht ist.f! ./ Semiconductor arrangement, in particular integrated semiconductor circuit arrangement with at least one insulation 3 chich / fc on the semiconductor base body, characterized g e 3: indicates that the insulation layer is a Titanium oxide layer is. 2. Verfahren zur Herstellung der Isolationsschicht nach Anspruch 1, gekennzeichnet durch folgende Verfahrensschritte:2. A method for producing the insulation layer according to claim 1, characterized by the following Process steps: a) Aufbringen einer Titanschicht auf den Halbleitergrundkörper ,a) application of a titanium layer to the semiconductor base body, b) Oxydieren der Titanschicht zu der Titanoxidschicht.b) oxidizing the titanium layer to form the titanium oxide layer. 3. Verfahren nach Anspruch 2, dadurch gekennzeichnet , daß die Titanschicht in einer Dicke bis zu 0,5 /um auf den Halbleitergrundkörper aufgedampft wird.3. The method according to claim 2, characterized in that the titanium layer in a thickness of up to 0.5 / µm is vapor-deposited onto the semiconductor base body. 4. Verfahren nach Anspruch 2 oder 3, dadurch gekennzeichnet , daß die Titanschicht in Wasserstoffsuperoxid bei etwa 107 0G während etwa 10 Minuten zu der Titanoxidschicht oxidiert wird.4. The method according to claim 2 or 3, characterized in that the titanium layer is oxidized in hydrogen peroxide at about 107 0 G for about 10 minutes to form the titanium oxide layer. 5. Vorfahren nach Anspruch 2 oder 3, dadurch gekennzeichnet, daß die Titanschicht in Salpetersäure zu der Titanoxidschicht oxidiert wird.5. Ancestors according to claim 2 or 3, characterized in that that the titanium layer is oxidized in nitric acid to form the titanium oxide layer. 6. Verfahren zum bereichsweisen Aufbringen der Isolationsschicht auf den Halbleitergrundkörper nach einem der Ansprüche 2-5, gekennzeichnet durch folgende Verfahrensschritte;6. A method for applying the insulation layer in regions to the semiconductor base body according to one of the claims 2-5, characterized by the following process steps; a) Aufbringen der Titanschicht auf den Halbleitergrundkörper,a) application of the titanium layer to the semiconductor base body, b) Aufbringen einer Goldschicht auf die Titanschicht,b) applying a gold layer to the titanium layer, c) Entfernen der Goldschicht entsprechend der gewünschtenc) Remove the gold layer according to the desired 109835/1379109835/1379 VPA 9/110/0018 - 8 -VPA 9/110/0018 - 8 - Struktur mittels Fototechnik,Structure using photo technology, d) Oxidieren eier dadurch freigelegten Bereiche der Titan-Gchicht au der Titanoxidschicht.d) Oxidation of the areas of the titanium layer exposed as a result on the titanium oxide layer. 7· Verfahren nach Anspruch 6, dadurch gekennzeichnet, da!2 die nicht freigelegten Bereiche der Titanschicht in Verbindung mit in dem Halbleitergrundkörper angeordneten Kontaktflecken vorgesehen werden.7. The method according to claim 6, characterized in that because! 2 the unexposed areas of the titanium layer in connection with in the semiconductor base body arranged contact pads are provided. ö. Verfahren zur Ausbildung einer weiteren Leitbahnebene auf einen mit einer Leitbahnebene versehenen Halbleitergrundkörper nach einem der Ansprüche 2-7, dadurch gekennzeichnet, daß als Isolationsschicht zwischen den Leitbahnebenen eine Titanoxidschicht verwendet wird, und daß zur elektrischen Verbindung zwischen Kontakten der einen Leitbahnebene und der weiteren Leitbahnebene eine Titanochicht verwendet wird.ö. Procedure for the formation of a further channel level a semiconductor base body provided with an interconnect plane according to one of claims 2-7, characterized in that as an insulation layer between the interconnect planes a titanium oxide layer is used, and that for the electrical connection between contacts the one interconnect level and the other interconnect level a titanium layer is used. 9. Verfahren nach Anspruch 6, dadurch gekennzeichnet , daß die Titarioxidschicht durch bereichsweise Oxidation der Titanschicht gebildet wird.9. The method according to claim 6, characterized that the titanium oxide layer is formed by partial oxidation of the titanium layer. 109835/1379 ORIGINAL INSPECTED109835/1379 ORIGINAL INSPECTED
DE19702006703 1970-02-13 1970-02-13 Insulation layer on a semiconductor base body Pending DE2006703A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
DE19702006703 DE2006703A1 (en) 1970-02-13 1970-02-13 Insulation layer on a semiconductor base body
CH170671A CH522960A (en) 1970-02-13 1971-02-05 Semiconductor arrangement with at least one insulation layer
AT102271A AT327291B (en) 1970-02-13 1971-02-08 METHOD OF APPLYING AN INSULATING LAYER OF TITANOXYDE ON A SEMICONDUCTOR BODY
FR7104399A FR2079406B1 (en) 1970-02-13 1971-02-10
NL7101934A NL7101934A (en) 1970-02-13 1971-02-12
CA105,339A CA970257A (en) 1970-02-13 1971-02-13 Insulating layer on a semiconductor substrate
SE01919/71A SE365900B (en) 1970-02-13 1971-02-15
GB2166171A GB1312183A (en) 1970-02-13 1971-04-19 Semiconductor arrangements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19702006703 DE2006703A1 (en) 1970-02-13 1970-02-13 Insulation layer on a semiconductor base body

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DE2006703A1 true DE2006703A1 (en) 1971-08-26

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DE19702006703 Pending DE2006703A1 (en) 1970-02-13 1970-02-13 Insulation layer on a semiconductor base body

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AT (1) AT327291B (en)
CA (1) CA970257A (en)
CH (1) CH522960A (en)
DE (1) DE2006703A1 (en)
FR (1) FR2079406B1 (en)
GB (1) GB1312183A (en)
NL (1) NL7101934A (en)
SE (1) SE365900B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2188308B1 (en) * 1972-06-02 1977-04-01 Thomson Csf
NL184184C (en) * 1981-03-20 1989-05-01 Philips Nv METHOD FOR APPLYING CONTACT INCREASES TO CONTACT PLACES OF AN ELECTRONIC MICROCKETES

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NL7101934A (en) 1971-08-17
FR2079406B1 (en) 1976-10-29
AT327291B (en) 1976-01-26
CA970257A (en) 1975-07-01
CH522960A (en) 1972-05-15
GB1312183A (en) 1973-04-04
SE365900B (en) 1974-04-01
ATA102271A (en) 1975-04-15
FR2079406A1 (en) 1971-11-12

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