DE19946203B4 - Support structure for a stacked foot arrangement - Google Patents
Support structure for a stacked foot arrangement Download PDFInfo
- Publication number
- DE19946203B4 DE19946203B4 DE19946203A DE19946203A DE19946203B4 DE 19946203 B4 DE19946203 B4 DE 19946203B4 DE 19946203 A DE19946203 A DE 19946203A DE 19946203 A DE19946203 A DE 19946203A DE 19946203 B4 DE19946203 B4 DE 19946203B4
- Authority
- DE
- Germany
- Prior art keywords
- support structure
- gate conductor
- insulator layer
- metal
- metal track
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Stützstruktur für eine gestapelte Fuseanordnung, bei der eine Metallbahn (7) auf einer unteren Metallisierungsebene über ein Kontaktloch (11) mit einer Fuse (12) auf einer oberen Metallisierungsebene verbunden ist und die Metallbahn (7) auf einer Isolatorschicht (3) geführt ist, in die ein Gateleiter (5) eingebettet ist, dadurch gekenneichnet, dass der Gateleiter (5) eine sich senkrecht zu seiner Längsrichtung erstreckende Ausdehnung aufweist, die sich zum Stützen der Metallbahn (7) direkt unterhalb von dieser in der Isolatorschicht (3) bis in einen Bereich unterhalb des Kontaktloches (11) erstreckt.Support structure for a stacked fuse arrangement, in which a metal track (7) on a lower metallization level is connected via a contact hole (11) to a fuse (12) on an upper metallization level and the metal track (7) is guided on an insulator layer (3), in which a gate conductor (5) is embedded, characterized in that the gate conductor (5) has an extension extending perpendicular to its longitudinal direction, which is used to support the metal strip (7) directly below it in the insulator layer (3) to in extends an area below the contact hole (11).
Description
Die vorliegende Erfindung betrifft eine Stützstruktur für eine gestapelte Fuseanordnung, bei der eine Metallbahn auf einer unteren Metallisierungsebene über ein Kontaktloch mit einer Fuse auf einer oberen Metallisierungsebene verbunden ist und die Metallbahn auf einer Isolatorschicht geführt ist, in die ein Gateleiter eingebettet ist.The present invention relates to a support structure for one stacked fuse arrangement with a metal sheet on a lower one Metallization level above a contact hole with a fuse on an upper metallization level is connected and the metal track is guided on an insulator layer, in which a gate conductor is embedded.
In der
Wie nun in der
Wird sodann zur Bildung von Fuses
eine weitere Metallschicht in einer höheren Metallisierungsebene
("M1") aufgetragen und
werden die Fuses in dieser höheren
Ebene geschossen, so können
die Metallreste
Es ist daher Aufgabe der vorliegenden Erfindung, eine Stützstruktur für eine gestapelte Fuseanordnung zu schaffen, welche das Auftreten von Metallresten zuverlässig zu verhindern vermag.It is therefore the task of the present Invention, a support structure for one to create stacked fuse arrangement which prevents the occurrence of metal residues reliable is able to prevent.
Diese Aufgabe wird bei einer Stützstruktur der eingangs genannten Art erfindungsgemäß dadurch gelöst, daß der Gateleiter eine sich senkrecht zu seiner Längsrichtung erstreckende Ausdehnung aufweist, die sich zum Stützen der Metallbahn direkt unterhalb von dieser in der Isolatorschicht bis in einen Bereich unterhalb des Kontaktlochs erstreckt.This task is carried out with a support structure initially mentioned type solved according to the invention in that the gate conductor one perpendicular to its longitudinal direction extending extent, which is used to support the Metallbahn directly below this in the insulator layer up extends into an area below the contact hole.
Der Gateleiter kann dabei aus dotiertem polykristallinem Silizium bestehen. Außerdem kann sich der Gateleiter ausgehend von einem Gatering in dessen Innenraum erstrecken.The gate conductor can be made of doped polycrystalline silicon exist. The gate conductor can also starting from a catering in its interior.
Die Erfindung geht damit einen von bisherigen Versuchen zur Lösung der obigen Problemstellung vollkommen abweichenden Weg: Es wird nämlich nicht länger versucht, das sogenannte "Prozeßfenster" bei der Gestaltung des Innenraumes des Gateringes zu optimieren, um das Auftreten der "Delle" zu vermeiden. Vielmehr wird zur Verhinderung einer solchen "Delle" der Gateleiter unter die Metallbahn ("M0-Bahn") gelegt, ob wohl der Gateleiter hier keine elektrische Funktion zu erfüllen hat. Er dient unterhalb der Metallbahn lediglich als "Stützstruktur", die das Auftreten einer "Delle" verhindert. Hierdurch wird ein gleichmäßiges chemisch-mechanisches Polieren ermöglicht, das keine tiefen "Dellen" bzw. Mulden hinterläßt, in welchen sich Metallreste ansammeln können. Die Stützstruktur wird so in vorteilhafter Weise an solchen Stellen einge fügt, welche dem Fuse-Prozeß unterhalb der untersten Metallisierungsebene nicht stören.The invention is one of previous attempts to solve completely different way from the problem above: It will namely no longer tried to design the so-called "process window" to optimize the interior of the catering in order to avoid the appearance of the "dent". Much more to prevent such a "dent" of the gate conductor under the metal track ("M0-Bahn") placed whether well the gate conductor has no electrical function to perform here. It only serves as a "support structure" below the metal track, which is the occurrence a "dent" prevented. This will an even chemical-mechanical Polishing enables that doesn't leave deep "dents" or hollows in which metal residues can accumulate. The support structure is thus inserted in an advantageous manner at those points which the fuse process below the lowest level of metallization.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention is explained below the drawings closer explained. Show it:
Die
Außerdem sind in
Die Isolatorschichten
Die erfindungsgemäße Stützstruktur läßt sich
auf einfache Weise herstellen, da für die Ausbildung der Ausdehnungen
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19946203A DE19946203B4 (en) | 1999-09-27 | 1999-09-27 | Support structure for a stacked foot arrangement |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19946203A DE19946203B4 (en) | 1999-09-27 | 1999-09-27 | Support structure for a stacked foot arrangement |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19946203A1 DE19946203A1 (en) | 2001-04-19 |
DE19946203B4 true DE19946203B4 (en) | 2004-05-06 |
Family
ID=7923419
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19946203A Expired - Fee Related DE19946203B4 (en) | 1999-09-27 | 1999-09-27 | Support structure for a stacked foot arrangement |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE19946203B4 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5254497A (en) * | 1992-07-06 | 1993-10-19 | Taiwan Semiconductor Manufacturing Company | Method of eliminating degradation of a multilayer metallurgy/insulator structure of a VLSI integrated circuit |
-
1999
- 1999-09-27 DE DE19946203A patent/DE19946203B4/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5254497A (en) * | 1992-07-06 | 1993-10-19 | Taiwan Semiconductor Manufacturing Company | Method of eliminating degradation of a multilayer metallurgy/insulator structure of a VLSI integrated circuit |
Also Published As
Publication number | Publication date |
---|---|
DE19946203A1 (en) | 2001-04-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |