DE1774929C3 - Monolithic memory cell with two cross-coupled transistors - Google Patents
Monolithic memory cell with two cross-coupled transistorsInfo
- Publication number
- DE1774929C3 DE1774929C3 DE19681774929 DE1774929A DE1774929C3 DE 1774929 C3 DE1774929 C3 DE 1774929C3 DE 19681774929 DE19681774929 DE 19681774929 DE 1774929 A DE1774929 A DE 1774929A DE 1774929 C3 DE1774929 C3 DE 1774929C3
- Authority
- DE
- Germany
- Prior art keywords
- collector
- case
- resistance
- memory cell
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 210000000352 storage cell Anatomy 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 210000004027 cell Anatomy 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 238000009415 formwork Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
- G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/8605—Resistors with PN junctions
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Description
Die Frfindung betrifft eine monolithisch integrierte Speicherzelle mit zwei kreuzgekoppelten Transistoren, su deren relativ hochohmigen Kollektorwiderständen in Form entsprechender Bhsisdiffusion des jeweils anderen Transistors je ein PN-Übergang als Diode mit besonderem Anschluß in der Basiszone parallel ge schaltet ist.The invention relates to a monolithically integrated memory cell with two cross-coupled transistors, see below their relatively high-resistance collector resistances in the form of corresponding Bhsisdiffusion of the respective other transistor with a PN junction as a diode special connection in the base zone is connected in parallel ge.
Schaltungen dieser Art sind äußerst vorteilhaft bei Anwendung einer Leistungsschaltung zur Adressierung, um eine an sich unvermeidliche Verlustleistung auf einem Minimum zu halten.Circuits of this type are extremely advantageous when using a power circuit for addressing, in order to keep an inherently unavoidable power loss to a minimum.
Sollen relativ hohe Schallgeschwindigkeiten angewendet werden, dann stellen sich infolge der als Dioden wirksamen PN-Übergänge insofern Nachteile ein. als der jeweilige Arbeitspunkt einer so gebildeten Diode nicht im günstigsten Bereich liegt.If relatively high speeds of sound are to be used, they turn out to be diodes effective PN junctions have disadvantages. than the respective operating point of a diode formed in this way is not in the most favorable range.
Die Aufgabe der Erfindung besteht nun darin, zur Korrektur der Lage des Arbeitspunktes beider Dioden Maßnahmen zu treffen, die ohne nennenswerten zusätzlichen Aufwand in einfacher Weise angewendet werden können.The object of the invention is to correct the position of the operating point of both diodes To take measures that are applied in a simple manner without significant additional effort can be.
Erfindungsgemäß wird diese Aufgabe für d:e oben beschriebene monolithisch integrierte Speicherzelle dadurch gelöst, daß jeweils der Kollektoranschluß zur BiI-dung eines relativ niederohmigen Widerstandes in Serie mit dem Kollektorwiderstand in entsprechender Entfernung vom Diodenanschluß angeordnet ist.According to the invention, this object is for d e above-described monolithically integrated memory cell achieved by the fact that in each case the collector terminal for BiI plication of a relatively low resistance in series with the collector resistance in a corresponding distance from the diode terminal is arranged.
Durch diese Maßnahmen ergeben sich nicht nur höhere anwendbare Schaltgeschwindigkeiten, sondern es zeiir* ich außerdem, da1} eine geringere Empfindlichkeit gegenüber Toleranzschwankungen eintritt.These measures not only result in higher applicable switching speeds, but also indicate that 1 } is less sensitive to tolerance fluctuations.
Eine besonders vorteilhafte Anwendung ergibt sich bei monolithischen Speicherzellen, bei der die Kolleklorwiderstände durch Pinchwiderständc, das ist jeweils bo ein unter Emittermaterial vergrabener Widerstand aus Basismaterial, dargestellt sind. In diesem Fall sieht die Lösung der Aufgabe derart aus, daß jeweils der Kollektor in der Kollektordiffusion in relativer Entfernung Vom Pinchwiderstand zur Ausnutzung des Epitaxie- f>5 Bahnwiderstandes kontaktiert ist.A particularly advantageous application results in monolithic storage cells in which the collector resistors by pinch resistors, that is in each case a resistor buried under the emitter material Base material, are shown. In this case the The object is achieved in such a way that the collector in each case is at a relative distance in the collector diffusion From the pinch resistance to the utilization of the epitaxial f> 5 Railway resistance is contacted.
Mit dieser Maßnahme lassen sich die angegebenen Vorteile erzielen, ohne daß ein wesentlich größererWith this measure, the specified advantages can be achieved without a significantly greater one
929 2 929 2
Platzbedarf im Layout erforderlich ist, als es für die monolithisch integrierte Speicherzelle an sich notwen-Space is required in the layout than is necessary for the monolithically integrated memory cell per se.
Weitere Vorteite%r Erfindung ergeben sich aus der nachfolgenden Beschreibung, die an Hand eines Ausffihrungsbcispiels mit Hilfe der nachstehend aufgeführten Zeichnungen die Erfindung näher erläutern soll, und aus den Patentansprüchen. Es zfigtFurther advantages result from the invention following description, based on an exemplary embodiment to explain the invention in more detail with the help of the drawings listed below, and from the claims. It zfigt
F i g. 1 die Schaltung einer t-rfindungsgemäßen Speicherzelle.F i g. 1 the circuit of a t according to the invention Storage cell.
F i g. 2 das Layout einer Symmetnehälfte der Schaltung nach F i g. I undF i g. 2 the layout of one half of the symmetry of the circuit according to FIG. I and
F i g. 3 das Ersatzschaltbild einer SymmetriehälficF i g. 3 the equivalent circuit diagram of a symmetry half
Das hier beschriebene Ausführungsbeispiel einer Schaltung gemäß der Erfindung besteht aus zwei kreuzgekoppelten Multiemitteriransistoren, deren innere Emitter EIt ura E2\ miteinander verbunden sind und an konstantem Potential (OV) liegen, während die äußeren Emitter E12 und £22 an hier nicht gezeigten Abtastemrrchfungen einer aus Speicherzellen dieser An aufgebauten Speichermatrix liegen. Die Basis ll\ des einen Transistors ist mit dem Kollektor (.1 des an deren Transistors über die jeweiligen Diffusionen ein schließlich des PN Übergangs verbunden. Das gleiche gilt für die Basis Bl des anderen transistors und dm kollektor CX des einen Transistors. Die Kollekton.-n C l und Cl sind dabei jeweils über einen relativ nieJeroh migen Widerstand RXX bzw. RX2, im wesentlichen ge bildet aus den Bahnwiderständen der Kollek'or/onen. mit den relativ hochohmigen Kollektorwiderständen RcX b/w. R<2 verbunden, denen ihrerseits jeweils eine Diode DX bzw. Pl parallel liegt. Der gemeinsame Ver bindungspunkt der Kollektorwiderstände Rc\ und /?c2 liegt an der Anschlußklemme Vt.The exemplary embodiment of a circuit according to the invention described here consists of two cross-coupled multiemitter transistors, the inner emitters EIt ura E2 \ are connected to each other and at constant potential (OV) , while the outer emitters E12 and E22 are not shown here on scanning a memory cell this to built memory matrix lie. The base II of one transistor is connected to the collector (.1 of the other transistor via the respective diffusions including the PN junction. The same applies to the base B1 of the other transistor and the collector CX of one transistor. -n C l Cl and are in each case over a relatively nieJeroh-shaped resistance RXX or RX2, ge substantially forms the path resistances of the Kollek'or / ones. with the relatively high impedance collector resistors RCX b / w. R <2 connected, which in turn, a diode DX or P1 is parallel in each case. The common connection point of the collector resistors Rc \ and /? c2 is at the connection terminal Vt.
Die Realisierung einer solchen erfindungsgemäß aufgebauten Schaltung läßt sich an Hand des in I 1 g. 2 dargestellten Layouts beschreiben. Dieses Layout zeigt lediglich eine Symmetnehälfie der bistabilen Kippschalung nach F i g. 1 und läßt die wesentlichen Maßnahmen gemäii der Frfindung erkennen. Dabei stellt die äußere, mit P+ bezeichnete Umrandung die Isola tionswanne der dargestellten Symmetriehälfte dar. In dieser Isolationswanne befindet sich die mit N bezeichnete Kollektorschicht, die mit dem KollektoranschluU (2 oberhalb eines gestrichelt gezeichneten Subkollektors S kontaktiert ist. In diese Kollektorschicht N ist die Basiszone P eindiff'rndiert. die mit dem Basisanschluß Bl kontakliert ist Die Emitterzonen sind mit den Emitteranschlüssen £21 und £22 kontaktiert. Ein weiterer Anschluß Qdient zur Zuführung des Schaltimpulses bei der Adressierung. Zur Bereitstellung eines Pinchwiderstandes ist zwischen dem Anschluß Q und dem Basisanschluß Bl eine, die Basiszone überdeckende. N+-Zone aufgebracht, die zusätzlich seitlich mit der Kollektorzone N kontaktiert. Zwischen den Anschlüssen Q und Bl lie^t ein relativ huller Widerstand (einige 10 Kiloohm), bewirkt durch die geringe Stärke dieser Basisschicht. Zur Kollektorschicht Nund zur /V+ /ine existieren PN-Übergänge, die je nach Vorspannung entweder bei etwa 0,7 Volt leitend werden, oder im Sperrzustand bei etwa 7 Volt durchbrechen (Zcner-Durchbruch). The implementation of such a circuit constructed in accordance with the invention can be illustrated with the aid of the I 1 g. 2 describe the layouts shown. This layout shows only one half of the symmetry of the bistable tilting formwork according to FIG. 1 and reveals the essential measures according to the invention. The outer border, labeled P + , represents the insulation trough of the illustrated half of the symmetry. In this insulation trough is the collector layer marked N , which is in contact with the collector connection (2 above a subcollector S shown in dashed lines. In this collector layer N is the base zone P eindiff'rndiert. which is kontakliert to the base terminal Bl the emitter regions are in contact with the emitter terminals of £ 21 and £ 22nd Another terminal Q is used for the supply of the switching pulse in the addressing. to provide a Pinchwiderstandes is connected between the Q terminal and the base terminal Bl applied a, the base region covering. N + region which additionally contacted side with the collector region N. between the terminals Q and Bl lie ^ t a relatively huller resistance (some 10 ohms), caused by the low strength of this base layer. to collector layer N and to / V + / ine exist PN junctions, each of which is na The bias voltage either becomes conductive at around 0.7 volts, or breaks through in the off-state at around 7 volts (Zcner breakdown).
In der Stromspannungskennlinie zwischen den Anschlüssen Q und 02 liegi zunächst ein ohmschcr Bereich für einen Spannungsabfall unter 0,7 Voll vor, wohingegen bei Überschreiten dieses Wertes aber der PN-Übergang leitend wird, der die höchste Potcntialdiffercrtz aufweist — bei Stromfluß von ζ)nach Bl, alsoIn the current- voltage characteristic between the connections Q and 02 there is initially an ohmic range for a voltage drop below 0.7 full, whereas when this value is exceeded the PN junction becomes conductive, which has the highest potential difference - with a current flow of ζ) according to Bl , so
der PN-Übergang zwischen Q und N+. Es ergibt sich demnach ein Stromfluß entsprechend einer Diodenkennlinie. so daß mit Hilfe eines Pinchwiderstandes die Serienschallung einer Diode und eines relativ hohen Widerstandes realisiert wird, die zwischen Kollektor Cl und Basis Bl geschaltet ist.the PN junction between Q and N +. The result is a current flow corresponding to a diode characteristic. so that with the help of a pinch resistor, the series sound of a diode and a relatively high resistance is realized, which is connected between collector Cl and base B1 .
Dadurch, daß aber der Kollektoranschluß sich nicht auf der N + -Zone befindet, sondern außerhalb der Basiszone über dem Subkollektor Sin Torrn des Anschlusses Cl. wird diese Serienschaliung. wie nachstehend erläutert, nocL ergänzt.Because the collector connection is not located on the N + zone, but rather outside the base zone via the subcollector Sin Torrn of the connection Cl. is this serial formwork. as explained below, nocL added.
Hieraus ergibt sich nämlich, daß die beiden nicderohmigeii Vorwiderständc All und R\2 als Bahn widerstände in der Kollcklorsehicht zwischen Pinchwiderstand und dem wirksamen Kollektorbereich über dem Subkollektor S realisiert sind.From this it follows that the two nicderohmigeii series resistors All and R \ 2 are implemented as path resistances in the collision layer between the pinch resistor and the effective collector area above the subcollector S.
An Hand des Ersatzschaltbildes in Y i g. 3 für eine Synmetriehälfte soll nun die Betriebsweise der F.rfin dung näher erläutert werden. Im Ruhezustand der Speicherzelle sind die Dioden Di und £32 schwach leitend bzw. gesperrt, so daß der Spannungsabfall an den niederohmigen Widerständen All und #12 vernachlässigbar ist. Im adressierten Zustand wird das Potential im Punkt Q soweit angehoben, daß die Dioden Dl und D2 in beiden KoUektorzweigen in einen gutleitenden Zustand überj !cn. Der Betriebszustand der Speicherzelle entspricht jetzt einer solchen mit niederohmigen KoUektorwiderständen, so daß die Spannungsabfalls an den Dioden etwa gleich sind.Using the equivalent circuit diagram in Y i g. 3, the mode of operation of the invention will now be explained in more detail for one half of the symmetry. When the memory cell is in the idle state, the diodes Di and £ 32 are weakly conductive or blocked, so that the voltage drop across the low-resistance resistors All and # 12 is negligible. In the addressed state, the potential at point Q is raised to such an extent that the diodes D1 and D2 in both connector branches switch to a conductive state. The operating state of the memory cell now corresponds to one with low-ohmic co-uector resistances, so that the voltage drops across the diodes are approximately the same.
Mierdings ist der Strom durch den Kollektorzweig mit leitendem Transistor höher, so daß sich ein SpannungsunterschJüd zwischen den beiden Kollektoren der Transistoren ergibt. Die Bedingung für stabiles Arbei-However, the current through the collector branch with the conducting transistor is higher, so that there is a voltage difference between the two collectors of the transistors results. The condition for stable work
lu ten der Speicherzelle erfordert nun, daß dieser Spannungsunterschied ausreichend hoch ist. Dadurch, daß in der erfindungsgemäßen Schaltung dank der Verwendung der niederohmigen Widerstände Ri 1 und R12 die beiden Dioden relativ rasch in einen gut leitenden Zustand übergehen, iassen sich höhere Schaltgeschwindig keiten erzielen, indem sich gleichzeitig eine geringere Empfindlichkeit gegenüber Toleranzschwankungen ergibt. Lu th of the memory cell now requires that this voltage difference is sufficiently high. The fact that in the circuit according to the invention, thanks to the use of the low resistance Ri 1 and R12, the two diodes pass relatively quickly into a highly conductive state, higher switching speeds can be achieved while at the same time there is less sensitivity to tolerance fluctuations.
In vorteilhafter Ausgestaltung der Erfindung wird durch die besondere Anordnung der Anschlußkontakte ein epitaxialer Widerstand zwischen dem Punkt O und dem Kollcktoranschluß Cl bzw. C^ wirksam; dabei ist es dann von besonderem Vorteil, daß der Plaizbedarf nicht wesentlich erhöht wird.In an advantageous embodiment of the invention, due to the special arrangement of the connection contacts, an epitaxial resistance between the point O and the collector connection C1 or C ^ becomes effective; It is then of particular advantage that the planning requirement is not significantly increased.
Hierzu 1 Blatt Zeichnungen1 sheet of drawings
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19681774929 DE1774929C3 (en) | 1968-03-01 | 1968-03-01 | Monolithic memory cell with two cross-coupled transistors |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1574651*CA DE1574651C3 (en) | 1968-03-01 | 1968-03-01 | Monolithically integrated flip-flop memory cell |
| DE19681774929 DE1774929C3 (en) | 1968-03-01 | 1968-03-01 | Monolithic memory cell with two cross-coupled transistors |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| DE1774929A1 DE1774929A1 (en) | 1971-11-04 |
| DE1774929B2 DE1774929B2 (en) | 1975-01-16 |
| DE1774929C3 true DE1774929C3 (en) | 1975-09-04 |
Family
ID=25753158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19681774929 Expired DE1774929C3 (en) | 1968-03-01 | 1968-03-01 | Monolithic memory cell with two cross-coupled transistors |
Country Status (1)
| Country | Link |
|---|---|
| DE (1) | DE1774929C3 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2510593C3 (en) * | 1975-03-11 | 1982-03-18 | Siemens AG, 1000 Berlin und 8000 München | Integrated semiconductor circuit arrangement |
| DE2739283A1 (en) * | 1977-08-31 | 1979-03-15 | Siemens Ag | INTEGRATED SEMICONDUCTOR STORAGE CELL |
-
1968
- 1968-03-01 DE DE19681774929 patent/DE1774929C3/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE1774929B2 (en) | 1975-01-16 |
| DE1774929A1 (en) | 1971-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE1524838A1 (en) | Information store | |
| DE2217456B2 (en) | Transistor circuit with anti-saturation circuit | |
| DE1942559B2 (en) | Storage facility for information | |
| DE2514466B2 (en) | INTEGRATED SEMI-CONDUCTOR CIRCUIT | |
| DE1943302B2 (en) | INTEGRATED, SELF-ISOLATING TRANSISTOR ARRANGEMENT | |
| DE1524873B2 (en) | Monolithic integrated storage cell with low quiescent power | |
| DE10308323B4 (en) | Semiconductor chip arrangement with ROM | |
| DE1574651C3 (en) | Monolithically integrated flip-flop memory cell | |
| DE1774929C3 (en) | Monolithic memory cell with two cross-coupled transistors | |
| DE1764241C3 (en) | Monolithically integrated semiconductor circuit | |
| DE2736324C2 (en) | Logical combination circuit | |
| DE1937853C3 (en) | Integrated circuit | |
| DE3507181A1 (en) | Circuit arrangement for avoiding parasitic substrate effects in integrated circuits | |
| DE2263075C3 (en) | Electrical power supply for a monolithically integrated semiconductor arrangement | |
| DE2259432A1 (en) | NPN-PNP-TRANSISTOR-SEMICONDUCTOR MEMORY WITH TWO CONNECTIONS | |
| DE3033731C2 (en) | Static bipolar memory cell and memory made up of such cells | |
| DE69227106T2 (en) | Structure to prevent the switching through of a parasitic diode located in an epitaxial well of integrated circuits | |
| DE2357332A1 (en) | INTEGRATED CIRCUIT | |
| DE2108419C3 (en) | Flip-flop memory cell | |
| DE4040070C2 (en) | PNP transistor with a protective element to protect against static electricity | |
| DE3021565A1 (en) | FLIP-FLOP | |
| DE2442773A1 (en) | INTEGRATED MASTER-SLAVE FLIP-FLOP | |
| EP0139027B1 (en) | Monolithic integrated circuit with at least one integrated resistor | |
| EP0017668B1 (en) | Programmable logic circuitry | |
| DE2055661B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C3 | Grant after two publication steps (3rd publication) | ||
| E77 | Valid patent as to the heymanns-index 1977 | ||
| EHJ | Ceased/non-payment of the annual fee |