DE10318603B4 - Eingangsempfängerschaltung - Google Patents
Eingangsempfängerschaltung Download PDFInfo
- Publication number
- DE10318603B4 DE10318603B4 DE10318603A DE10318603A DE10318603B4 DE 10318603 B4 DE10318603 B4 DE 10318603B4 DE 10318603 A DE10318603 A DE 10318603A DE 10318603 A DE10318603 A DE 10318603A DE 10318603 B4 DE10318603 B4 DE 10318603B4
- Authority
- DE
- Germany
- Prior art keywords
- output signals
- high speed
- processed
- reception circuit
- input reception
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10318603A DE10318603B4 (de) | 2003-04-24 | 2003-04-24 | Eingangsempfängerschaltung |
US10/831,001 US7477717B2 (en) | 2003-04-24 | 2004-04-23 | Input receiver circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10318603A DE10318603B4 (de) | 2003-04-24 | 2003-04-24 | Eingangsempfängerschaltung |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10318603A1 DE10318603A1 (de) | 2004-12-09 |
DE10318603B4 true DE10318603B4 (de) | 2005-03-10 |
Family
ID=33440611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10318603A Expired - Fee Related DE10318603B4 (de) | 2003-04-24 | 2003-04-24 | Eingangsempfängerschaltung |
Country Status (2)
Country | Link |
---|---|
US (1) | US7477717B2 (de) |
DE (1) | DE10318603B4 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6515914B2 (en) * | 2001-03-21 | 2003-02-04 | Micron Technology, Inc. | Memory device and method having data path with multiple prefetch I/O configurations |
US8037272B2 (en) * | 2007-06-27 | 2011-10-11 | International Business Machines Corporation | Structure for memory chip for high capacity memory subsystem supporting multiple speed bus |
US7921264B2 (en) * | 2007-06-27 | 2011-04-05 | International Business Machines Corporation | Dual-mode memory chip for high capacity memory subsystem |
US8019949B2 (en) * | 2007-06-27 | 2011-09-13 | International Business Machines Corporation | High capacity memory subsystem architecture storing interleaved data for reduced bus speed |
US7818512B2 (en) * | 2007-06-27 | 2010-10-19 | International Business Machines Corporation | High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules |
US7921271B2 (en) * | 2007-06-27 | 2011-04-05 | International Business Machines Corporation | Hub for supporting high capacity memory subsystem |
US8037270B2 (en) * | 2007-06-27 | 2011-10-11 | International Business Machines Corporation | Structure for memory chip for high capacity memory subsystem supporting replication of command data |
US7809913B2 (en) * | 2007-06-27 | 2010-10-05 | International Business Machines Corporation | Memory chip for high capacity memory subsystem supporting multiple speed bus |
US7996641B2 (en) * | 2007-06-27 | 2011-08-09 | International Business Machines Corporation | Structure for hub for supporting high capacity memory subsystem |
US8037258B2 (en) * | 2007-06-27 | 2011-10-11 | International Business Machines Corporation | Structure for dual-mode memory chip for high capacity memory subsystem |
US7822936B2 (en) * | 2007-06-27 | 2010-10-26 | International Business Machines Corporation | Memory chip for high capacity memory subsystem supporting replication of command data |
US20090006774A1 (en) * | 2007-06-27 | 2009-01-01 | Gerald Keith Bartley | High Capacity Memory Subsystem Architecture Employing Multiple-Speed Bus |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58161524A (ja) * | 1982-03-19 | 1983-09-26 | Seiko Instr & Electronics Ltd | 容量可変回路 |
DE69006634T2 (de) * | 1989-04-27 | 1994-05-26 | Telefonaktiebolaget L M Ericsson, Stockholm | Verfahren und Vorrichtung zum Vermeiden falscher Echoelimination und/oder zum Vermeiden falscher Entzerrung in einem Telekommunikationssystem. |
JP2002217695A (ja) * | 2001-01-16 | 2002-08-02 | Matsushita Electric Ind Co Ltd | 半導体集積回路およびノイズ除去回路の制御方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5400026A (en) * | 1993-08-23 | 1995-03-21 | Hypres, Inc. | Flash analog-to-digital converter employing Josephson junctions |
US6484269B1 (en) * | 1995-11-09 | 2002-11-19 | Emc Corporation | Data storage system and method with improved data integrity value calculation |
US5939895A (en) * | 1997-06-13 | 1999-08-17 | Trw Inc. | Frozen wave high speed receiver |
US6292116B1 (en) * | 1999-05-17 | 2001-09-18 | Altera Corporation | Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit |
JP3705102B2 (ja) * | 2000-09-14 | 2005-10-12 | 日本電気株式会社 | 通信装置 |
TW569536B (en) * | 2001-09-05 | 2004-01-01 | Elantec Semiconductor Inc | Analog demultiplexer |
-
2003
- 2003-04-24 DE DE10318603A patent/DE10318603B4/de not_active Expired - Fee Related
-
2004
- 2004-04-23 US US10/831,001 patent/US7477717B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58161524A (ja) * | 1982-03-19 | 1983-09-26 | Seiko Instr & Electronics Ltd | 容量可変回路 |
DE69006634T2 (de) * | 1989-04-27 | 1994-05-26 | Telefonaktiebolaget L M Ericsson, Stockholm | Verfahren und Vorrichtung zum Vermeiden falscher Echoelimination und/oder zum Vermeiden falscher Entzerrung in einem Telekommunikationssystem. |
JP2002217695A (ja) * | 2001-01-16 | 2002-08-02 | Matsushita Electric Ind Co Ltd | 半導体集積回路およびノイズ除去回路の制御方法 |
Also Published As
Publication number | Publication date |
---|---|
US7477717B2 (en) | 2009-01-13 |
US20040260964A1 (en) | 2004-12-23 |
DE10318603A1 (de) | 2004-12-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE |
|
8339 | Ceased/non-payment of the annual fee |