DE102012219622B4 - Micro-technological component with bonded connection - Google Patents

Micro-technological component with bonded connection Download PDF

Info

Publication number
DE102012219622B4
DE102012219622B4 DE102012219622.6A DE102012219622A DE102012219622B4 DE 102012219622 B4 DE102012219622 B4 DE 102012219622B4 DE 102012219622 A DE102012219622 A DE 102012219622A DE 102012219622 B4 DE102012219622 B4 DE 102012219622B4
Authority
DE
Germany
Prior art keywords
layer
substrate
component
intermediate layer
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102012219622.6A
Other languages
German (de)
Other versions
DE102012219622A1 (en
Inventor
Julian Gonska
Heribert Weber
Thomas Mayer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE102012219622.6A priority Critical patent/DE102012219622B4/en
Publication of DE102012219622A1 publication Critical patent/DE102012219622A1/en
Application granted granted Critical
Publication of DE102012219622B4 publication Critical patent/DE102012219622B4/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01CMEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C19/00Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
    • G01C19/56Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
    • G01C19/5642Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using vibrating bars or beams
    • G01C19/5663Manufacturing; Trimming; Mounting; Housings
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01PMEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0802Details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05023Disposition the whole internal layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671Chromium [Cr] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681Tantalum [Ta] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/05686Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05687Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13006Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13562On the entire exposed surface of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13563Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13565Only outside the bonding interface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605Shape
    • H01L2224/16057Shape in side view
    • H01L2224/16058Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165Material
    • H01L2224/16505Material outside the bonding interface, e.g. in the bulk of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29005Structure
    • H01L2224/29006Layer connector larger than the underlying bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/2901Shape
    • H01L2224/29016Shape in side view
    • H01L2224/29018Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • H01L2224/29082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29075Plural core members
    • H01L2224/2908Plural core members being stacked
    • H01L2224/29083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29109Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/2956Disposition
    • H01L2224/29562On the entire exposed surface of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/2956Disposition
    • H01L2224/29563Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/29565Only outside the bonding interface of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/29599Material
    • H01L2224/296Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954Coating
    • H01L2224/29599Material
    • H01L2224/296Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • H01L2224/32058Shape in side view being non uniform along the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325Material
    • H01L2224/32505Material outside the bonding interface, e.g. in the bulk of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81805Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/8182Diffusion bonding
    • H01L2224/81825Solid-liquid interdiffusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83193Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/83805Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • H01L2224/8382Diffusion bonding
    • H01L2224/83825Solid-liquid interdiffusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600, 700) mit einem ersten Substrat (110),wobei auf dem ersten Substrat (110) eine erste Schicht (130, 530) angeordnet ist,wobei zwischen dem ersten Substrat (110) und der ersten Schicht (130, 530) eine erste Zwischenschicht (120) angeordnet ist,wobei Seitenflächen (123) der ersten Zwischenschicht (120) durch eine Überdeckung (140, 540, 640) überdeckt sind,wobei zwischen der ersten Schicht (130, 530) und einer weiteren Schicht (370, 470) eine Bondverbindung (190) besteht,wobei die weitere Schicht (370, 470) eine auf einem zweiten Substrat (150) angeordnete zweite Schicht (370, 470) ist,wobei die erste Schicht (130, 530) und die zweite Schicht (370, 470) unterschiedliche Materialien aufweisen,wobei zwischen dem zweiten Substrat (150) und der zweiten Schicht (370, 470) eine zweite Zwischenschicht (360) angeordnet ist,wobei eine laterale Ausdehnung der zweiten Schicht (370, 470) größer als eine laterale Ausdehnung der zweiten Zwischenschicht (360) ist,wobei Randbereiche der zweiten Schicht (370, 470) eine zweite Überdeckung (380) bilden, die Seitenflächen (363) der zweiten Zwischenschicht (360) überdeckt.Microtechnological component (100, 200, 300, 400, 500, 600, 700) with a first substrate (110), wherein a first layer (130, 530) is arranged on the first substrate (110), wherein between the first substrate ( 110) and the first layer (130, 530), a first intermediate layer (120) is arranged, with side faces (123) of the first intermediate layer (120) being covered by a covering (140, 540, 640), with the first layer ( 130, 530) and a further layer (370, 470) there is a bond connection (190), the further layer (370, 470) being a second layer (370, 470) arranged on a second substrate (150), the first Layer (130, 530) and the second layer (370, 470) have different materials, a second intermediate layer (360) being arranged between the second substrate (150) and the second layer (370, 470), a lateral extension of the second layer (370, 470) greater than a lateral extent of the second intermediate ing layer (360), edge regions of the second layer (370, 470) forming a second covering (380) which covers side surfaces (363) of the second intermediate layer (360).

Description

Die Erfindung betrifft ein mikrotechnologisches Bauelement gemäß Patentanspruch 1 sowie ein Verfahren zum Herstellen eines mikrotechnologischen Bauelements gemäß Patentanspruch 9.The invention relates to a microtechnological component according to patent claim 1 and a method for producing a microtechnological component according to patent claim 9.

Stand der TechnikState of the art

Mikrotechnologische Bauelemente mit metallischen Bondverbindungen sind aus dem Stand der Technik bekannt. Solche Bondverbindungen können durch eutektische Materialsysteme (z.B. Aluminium/Germanium oder Gold/Silizium), homogene Materialsysteme für Thermokompressionsbonds (z.B. Aluminium, Kupfer oder Gold) und Transient-Liquid-Phase-Systeme (z.B. Kupfer/Zinn, Kupfer/Indium/Zinn oder Gold/Zinn) gebildet werden.Microtechnological components with metallic bonding connections are known from the prior art. Such bonds can be formed by eutectic material systems (e.g. aluminum/germanium or gold/silicon), homogeneous material systems for thermocompression bonds (e.g. aluminum, copper or gold) and transient liquid phase systems (e.g. copper/tin, copper/indium/tin or gold /tin) are formed.

Bei metallischen Bondflächen ist es bekannt, zwischen einem Substrat und der Bondfläche eine Zwischenschicht anzuordnen, die als Haftschicht die Haftung der Bondfläche auf dem Substrat verbessert und als Diffusionsbarriere eine Interdiffusion zwischen Metall und Substrat verhindert.In the case of metallic bonding surfaces, it is known to arrange an intermediate layer between a substrate and the bonding surface, which as an adhesive layer improves the adhesion of the bonding surface to the substrate and, as a diffusion barrier, prevents interdiffusion between the metal and the substrate.

Im Stand der Technik werden bei der Herstellung solcher mikrotechnologischer Bauelemente die Strukturierung der Zwischenschicht und die Strukturierung der Metallisierungsebene gemeinsam mit der gleichen Lackmaske durchgeführt. Hierdurch entstehen von außen zugängliche Seitenflächen der Zwischenschicht, die bei nachfolgenden Ätzschritten, etwa einem nachfolgenden HF-Gasphasenätzen, angegriffen werden können. Die dabei entstehende Unterätzung führt zu einer schlechteren Haftung des Materials auf dem Substrat und kann im Extremfall in Delamination enden.In the prior art, in the production of such microtechnology components, the structuring of the intermediate layer and the structuring of the metallization level are carried out together with the same resist mask. This gives rise to side faces of the intermediate layer which are accessible from the outside and which can be attacked in subsequent etching steps, for example subsequent HF gas-phase etching. The resulting undercut leads to poorer adhesion of the material to the substrate and, in extreme cases, can result in delamination.

Offenbarung der ErfindungDisclosure of Invention

Die Aufgabe der vorliegenden Erfindung besteht darin, ein verbessertes mikrotechnologisches Bauelement bereitzustellen. Diese Aufgabe wird durch ein mikrotechnologisches Bauelement mit den Merkmalen des Anspruchs 1 gelöst. Eine weitere Aufgabe der vorliegenden Erfindung besteht darin, ein verbessertes Verfahren zum Herstellen eines mikrotechnologischen Bauelements anzugeben. Diese Aufgabe wird durch ein Verfahren mit den Merkmalen des Anspruchs 9 gelöst. Bevorzugte Weiterbildungen sind in den abhängigen Ansprüchen angegeben.The object of the present invention is to provide an improved microtechnology component. This problem is solved by a microtechnological component with the features of claim 1 . A further object of the present invention consists in specifying an improved method for producing a microtechnical component. This object is achieved by a method having the features of claim 9. Preferred developments are specified in the dependent claims.

Ein erfindungsgemäßes mikrotechnologisches Bauelement umfasst ein erstes Substrat, auf dem eine erste Schicht angeordnet ist. Dabei ist zwischen dem ersten Substrat und der ersten Schicht eine erste Zwischenschicht angeordnet. Seitenflächen der ersten Zwischenschicht sind durch eine Überdeckung überdeckt. Dabei besteht zwischen der ersten Schicht und einer weiteren Schicht eine Bondverbindung. Durch die Überdeckung der Seitenflächen der Zwischenschicht ist diese vorteilhafterweise gegen einen Ätzangriff geschützt. Ein weiterer Vorteil kann darin bestehen, dass im Bereich der Überdeckung Material des Substrats in den Bereich der Bondverbindung diffundieren kann. Hierdurch kann eine Schmelztemperatur des Materialsystems erhöht werden. Dies kann während der Herstellung der eutektischen Bondverbindung dazu führen, dass Randbereiche der eutektischen Bondverbindung bereits vor innen gelegenen lateralen Bereichen der eutektischen Bondverbindung erstarren. Hierdurch wird einer lateralen Ausweitung der flüssigen Phase vorteilhafterweise entgegen gewirkt.A microtechnology component according to the invention comprises a first substrate on which a first layer is arranged. In this case, a first intermediate layer is arranged between the first substrate and the first layer. Side surfaces of the first intermediate layer are covered by an overlay. There is a bonding connection between the first layer and a further layer. By covering the side surfaces of the intermediate layer, this is advantageously protected against an etching attack. Another advantage can be that in the area of the covering, material of the substrate can diffuse into the area of the bond connection. As a result, a melting temperature of the material system can be increased. During the production of the eutectic bond connection, this can result in edge regions of the eutectic bond connection already solidifying before lateral regions of the eutectic bond connection located on the inside. This advantageously counteracts a lateral expansion of the liquid phase.

In einer Ausführungsform des mikrotechnologischen Bauelements weisen die erste Schicht und die Überdeckung Aluminium, mit Kupfer versetztes Aluminium (AICu), Kupfer, Gold oder Germanium auf. Vorteilhafterweise eignen sich diese Materialien zum Herstellen von Bondverbindungen.In one embodiment of the microtechnology component, the first layer and the covering comprise aluminum, aluminum mixed with copper (AICu), copper, gold or germanium. These materials are advantageously suitable for producing bonded connections.

Die weitere Schicht ist auf einem zweiten Substrat angeordnet. Dabei weisen die erste Schicht und die zweite Schicht unterschiedliche Materialien auf. Vorteilhafterweise kann zwischen den auf den Substraten angeordneten Schichten eine eutektische Bondverbindung ausgebildet sein.The further layer is arranged on a second substrate. In this case, the first layer and the second layer have different materials. A eutectic bond connection can advantageously be formed between the layers arranged on the substrates.

In einer weiteren Ausführungsform weist die erste Schicht mehrere Teilschichten auf. Beispielsweise kann die erste Schicht Kupfer und Zinn, Kupfer, Zinn und Indium oder Gold und Indium aufweisen. Die weitere Schicht ist dabei in Kupfer und Gold, Kupfer, Gold oder in gleicher Art wie die erste Schicht ausgebildet. Vorteilhafterweise kann zwischen den Schichten dann eine Transient-Liquid-Phase-Bondverbindung bestehen.In a further embodiment, the first layer has a plurality of sub-layers. For example, the first layer may include copper and tin, copper, tin and indium, or gold and indium. The further layer is made of copper and gold, copper, gold or in the same way as the first layer. A transient liquid phase bond connection can then advantageously exist between the layers.

Zwischen dem zweiten Substrat und der zweiten Schicht ist eine zweite Zwischenschicht angeordnet. Vorteilhafterweise kann die zweite Zwischenschicht als Haftschicht und als Diffusionsbarriere dienen. Dadurch verbessert sich die Haftung der zweiten Schicht auf dem zweiten Substrat. Außerdem wird vorteilhafterweise eine Diffusion von Material zwischen dem zweiten Substrat und der zweiten Schicht eingeschränkt.A second intermediate layer is arranged between the second substrate and the second layer. The second intermediate layer can advantageously serve as an adhesion layer and as a diffusion barrier. This improves the adhesion of the second layer to the second substrate. In addition, a diffusion of material between the second substrate and the second layer is advantageously restricted.

In einer bevorzugten Ausführungsform des mikrotechnologischen Bauelements wird die Überdeckung durch eine dritte Schicht gebildet. Dabei weisen die erste Schicht und die dritte Schicht unterschiedliche Materialien auf. Vorteilhafterweise kann es zwischen der ersten Schicht und der dritten Schicht dann bereits zu einer definierten Ausbildung einer eutektischen Schmelze kommen, ohne dass die erste Schicht mit der weiteren Schicht in Kontakt gebracht werden muss. Hierdurch können vorteilhafterweise kleine Unebenheiten und durch Kratzer oder Verschmutzungen verursachte Defekte ausgeglichen werden.In a preferred embodiment of the microtechnological component, the covering is formed by a third layer. The first layer and the third layer have different materials. Advantageously, a defined formation of a eutectic melt can then already occur between the first layer and the third layer, without the first layer being in contact with the further layer must be brought. In this way, small bumps and defects caused by scratches or dirt can advantageously be compensated.

In einer bevorzugten Ausführungsform des mikrotechnologischen Bauelements weist die erste Zwischenschicht Siliziumdioxid, Titan, Titannitrid, Tantal, Chrom oder Titanwolfram auf. Vorteilhafterweise wirkt die erste Zwischenschicht dann als Haftschicht und als Diffusionsbarriere. Die erste Schicht kann dann aus AI, AICu, Au und die zweite und dritte Schicht aus Si oder Ge bestehen.In a preferred embodiment of the microtechnological component, the first intermediate layer has silicon dioxide, titanium, titanium nitride, tantalum, chromium or titanium tungsten. The first intermediate layer then advantageously acts as an adhesive layer and as a diffusion barrier. The first layer can then consist of Al, AlCu, Au and the second and third layers of Si or Ge.

Ein erfindungsgemäßes Verfahren zum Herstellen eines mikrotechnologischen Bauelements umfasst Schritte zum Bereitstellen eines Substrats, zum Aufbringen einer Zwischenschicht auf dem Substrat, zum Aufbringen einer Metallschicht auf der Zwischenschicht, zum Überdecken der Seitenflächen der Zwischenschicht mit einer Überdeckung und zum eutektischen Bonden der Metallschicht an eine weitere Schicht. Vorteilhafterweise schützt das Überdecken der Seitenflächen der Zwischenschicht mit der Überdeckung die Seitenflächen vor einem Ätzangriff während eines nachfolgenden Ätzschritts, beispielsweise während eines HF-Gasphasenätzens.A method according to the invention for producing a microtechnological component comprises steps for providing a substrate, for applying an intermediate layer on the substrate, for applying a metal layer on the intermediate layer, for covering the side surfaces of the intermediate layer with a covering and for eutectic bonding of the metal layer to a further layer . Advantageously, covering the side surfaces of the intermediate layer with the covering protects the side surfaces from an etch attack during a subsequent etching step, for example during an HF gas phase etch.

In einer bevorzugten Ausführungsform des Verfahrens wird zwischen dem Überdecken der Seitenkanten und dem eutektischen Bonden ein Ätzprozess durchgeführt. Vorteilhafterweise wird durch die in einem vorhergehenden Schritt angelegte Überdeckung der Seitenflächen der Zwischenschicht verhindert, dass die Zwischenschicht während des Ätzprozesses über ihre Seitenflächen angegriffen werden kann.In a preferred embodiment of the method, an etching process is carried out between the covering of the side edges and the eutectic bonding. The covering of the side surfaces of the intermediate layer applied in a previous step advantageously prevents the intermediate layer from being attacked via its side surfaces during the etching process.

Die Erfindung wird nun anhand der beigefügten Figuren näher erläutert. Dabei zeigen in schematischer Darstellung:

  • 1 einen Schnitt durch einen Teil eines mikrotechnologischen Bauelements gemäß einer ersten Ausführungsform;
  • 2 einen weiteren Schnitt durch das mikrotechnologische Bauelement der ersten Ausführungsform;
  • 3 einen Schnitt durch ein mikrotechnologisches Bauelement einer zweiten Ausführungsform;
  • 4 einen Schnitt durch ein mikrotechnologisches Bauelement einer dritten Ausführungsform;
  • 5 einen Schnitt durch ein mikrotechnologisches Bauelement einer vierten Ausführungsform;
  • 6 einen Schnitt durch ein mikrotechnologisches Bauelement einer fünften Ausführungsform;
  • 7 einen Schnitt durch ein mikrotechnologisches Bauelement einer sechsten Ausführungsform; und
  • 8 einen Schnitt durch ein mikrotechnologisches Bauelement einer siebten Ausführungsform.
The invention will now be explained in more detail with reference to the accompanying figures. Shown in a schematic representation:
  • 1 a section through part of a micro-technological component according to a first embodiment;
  • 2 another section through the microtechnological component of the first embodiment;
  • 3 a section through a microtechnological component of a second embodiment;
  • 4 a section through a microtechnological component of a third embodiment;
  • 5 a section through a microtechnological component of a fourth embodiment;
  • 6 a section through a micro-technological component of a fifth embodiment;
  • 7 a section through a microtechnological component of a sixth embodiment; and
  • 8th a section through a microtechnological component of a seventh embodiment.

1 zeigt in stark schematisierter Darstellung einen Schnitt durch einen Teil eines mikrotechnologischen Bauelements 100 gemäß einer ersten Ausführungsform. Das mikrotechnologische Bauelement 100 kann ein mikromechanischer Sensor sein, beispielsweise ein Beschleunigungssensor, ein Drehratensensor oder ein anderer Inertialsensor. 1 FIG. 1 shows, in a highly schematic representation, a section through part of a microtechnological component 100 according to a first embodiment. The microtechnological component 100 can be a micromechanical sensor, for example an acceleration sensor, a yaw rate sensor or another inertial sensor.

Das mikrotechnologische Bauelement 100 weist ein erstes Substrat 110 auf. Das erste Substrat 110 kann beispielsweise ein Siliziumsubstrat sein. Auf einer Oberseite 111 des ersten Substrats 110 ist eine erste Zwischenschicht 120 angeordnet. Die erste Zwischenschicht 120 kann beispielsweise aus Siliziumdioxid, aus Titan, aus Titannitrid, aus Tantal, aus Chrom oder aus Titanwolfram bestehen. Die erste Zwischenschicht 120 weist eine Oberseite 121, eine Unterseite 122 und mehrere Seitenflächen 123 auf. Die Unterseite 122 der ersten Zwischenschicht 120 ist auf der Oberseite 111 des ersten Substrats 110 angeordnet. Die Oberseite 121 liegt der Unterseite 122 gegenüber. Die Seitenflächen 123 bilden Flanken, die die Oberseite 121 mit der Unterseite 122 der ersten Zwischenschicht 120 verbinden.The microtechnology component 100 has a first substrate 110 . The first substrate 110 can be a silicon substrate, for example. A first intermediate layer 120 is arranged on a top side 111 of the first substrate 110 . The first intermediate layer 120 can consist of silicon dioxide, titanium, titanium nitride, tantalum, chromium or titanium tungsten, for example. The first intermediate layer 120 has a top 121 , a bottom 122 and a plurality of side surfaces 123 . The bottom 122 of the first intermediate layer 120 is arranged on the top 111 of the first substrate 110 . The top 121 is the bottom 122 opposite. The side faces 123 form flanks that connect the top 121 to the bottom 122 of the first intermediate layer 120 .

Auf der Oberseite 121 der ersten Zwischenschicht 120 ist eine erste Schicht 130 angeordnet. Die erste Schicht 130 kann beispielsweise Aluminium, mit Kupfer versetztes Aluminium (AICu), Gold, Kupfer oder Germanium aufweisen. Die erste Schicht 130 kann auch mehrere Teilschichten umfassen, die beispielsweise Kupfer und Zinn, Kupfer, Zinn und Indium oder Gold und Indium aufweisen. Die erste Schicht 130 weist eine Oberseite 131 und eine Unterseite 132 auf. Die Unterseite 132 der ersten Schicht 130 ist auf der Oberseite 121 der ersten Zwischenschicht 120 angeordnet. Die erste Schicht 130 bildet ein Bondpad bzw. einen Bondrahmen, der dazu vorgesehen ist, mittels einer Bondverbindung mit einer weiteren Schicht verbunden zu werden.A first layer 130 is arranged on the upper side 121 of the first intermediate layer 120 . The first layer 130 may include, for example, aluminum, aluminum alloyed with copper (AICu), gold, copper, or germanium. The first layer 130 can also include a number of sub-layers which have, for example, copper and tin, copper, tin and indium or gold and indium. The first layer 130 has a top 131 and a bottom 132 . The bottom 132 of the first layer 130 is arranged on the top 121 of the first intermediate layer 120 . The first layer 130 forms a bond pad or a bond frame, which is intended to be connected to a further layer by means of a bond connection.

Die erste Zwischenschicht 120 dient als Haftschicht zur Verbesserung der Haftung der ersten Schicht 130 auf dem ersten Substrat 110. Außerdem dient die erste Zwischenschicht 120 als Diffusionsbarriere zwischen der ersten Schicht 130 und dem ersten Substrat 110. Durch das Vorhandensein der ersten Zwischenschicht 120 wird eine Diffusion des Materials des ersten Substrats 110 in die erste Schicht 130 und eine Diffusion des Materials der ersten Schicht 130 in das erste Substrat 110 im Bereich der Zwischenschicht 120 reduziert oder verhindert. Außerdem kann durch die erste Zwischenschicht 120 ein Übergangswiderstand zwischen dem ersten Substrat 110 und der ersten Schicht 130 gering gehalten werden. Die erste Zwischenschicht 120 kann weiter bewirken, dass sich der Übergangswiderstand etwa wie ein Ohmscher Widerstand verhält.The first intermediate layer 120 serves as an adhesion layer to improve the adhesion of the first layer 130 to the first substrate 110. The first intermediate layer 120 also serves as a diffusion barrier between the first layer 130 and the first substrate 110. The presence of the first intermediate layer 120 creates a diffusion of Material of the first substrate 110 in the first layer 130 and a diffusion of the material of the first layer 130 in the first substrate 110 in the region of the intermediate layer 120 is reduced or prevented. In addition, a contact resistance between the first substrate 110 and the first layer 130 can be kept low by the first intermediate layer 120 . The first intermediate layer 120 can also cause the contact resistance to behave approximately like an ohmic resistance.

Die erste Schicht 130 weist in lateraler Richtung (also parallel zur Oberseite 111 des ersten Substrats 110) eine größere Ausdehnung auf als die erste Zwischenschicht 120. Dadurch bilden über die erste Zwischenschicht 120 überstehende Teile der ersten Schicht 130 eine erste Überdeckung 140, die die Seitenflächen 123 der ersten Zwischenschicht 120 überdeckt und mit der Oberfläche 111 des ersten Substrats 110 in Kontakt steht. Die Seitenflächen 123 der ersten Zwischenschicht 120 sind somit nicht von außen zugänglich. Die erste Zwischenschicht 120 wird durch die erste Schicht 130 und das erste Substrat 110 vollständig umschlossen. Die erste Überdeckung 140 besteht aus demselben Material wie die übrigen Abschnitte der ersten Schicht 130 und weist etwa dieselbe Dicke auf wie die übrigen Abschnitte der ersten Schicht 130.The first layer 130 has a greater extent in the lateral direction (i.e. parallel to the upper side 111 of the first substrate 110) than the first intermediate layer 120. As a result, parts of the first layer 130 that project beyond the first intermediate layer 120 form a first covering 140, which covers the side surfaces 123 of the first intermediate layer 120 and is in contact with the surface 111 of the first substrate 110 . The side surfaces 123 of the first intermediate layer 120 are therefore not accessible from the outside. The first intermediate layer 120 is completely enclosed by the first layer 130 and the first substrate 110 . The first overlay 140 is made of the same material as the remaining portions of the first layer 130 and has approximately the same thickness as the remaining portions of the first layer 130.

Zur Herstellung der in 1 gezeigten Teile des mikrotechnologischen Bauelements 100 wurde zunächst das erste Substrat 110 mit der Oberseite 111 bereitgestellt. Auf der Oberseite 111 wurde die erste Zwischenschicht 120 abgeschieden. Anschließend wurde die erste Zwischenschicht 120 so strukturiert, dass die Seitenflächen 123 entstanden sind. Den Seitenflächen 123 benachbarte Abschnitte der ersten Zwischenschicht 120 wurden also von der Oberseite 111 des ersten Substrats 110 entfernt. Anschließend wurde die erste Schicht 130 auf der Oberseite 121 der ersten Zwischenschicht 120 und der Oberseite 111 des ersten Substrats 110 aufgebracht und strukturiert. In einem nachfolgenden Prozessschritt kann nun ein Ätzschritt, beispielsweise ein HF-Gasphasenätzen, erfolgen. Da die Seitenflächen 123 der ersten Zwischenschicht 120 durch die erste Überdeckung 140 geschützt sind, wird die erste Zwischenschicht 120 dabei nicht angegriffen.To produce the in 1 The parts of the microtechnical component 100 shown were initially provided with the first substrate 110 with the upper side 111 . The first intermediate layer 120 was deposited on the upper side 111 . The first intermediate layer 120 was then structured in such a way that the side surfaces 123 were created. Sections of the first intermediate layer 120 adjacent to the side surfaces 123 have therefore been removed from the upper side 111 of the first substrate 110 . Then the first layer 130 was applied and structured on the top side 121 of the first intermediate layer 120 and the top side 111 of the first substrate 110 . In a subsequent process step, an etching step, for example an HF gas phase etching, can now take place. Since the side faces 123 of the first intermediate layer 120 are protected by the first covering 140, the first intermediate layer 120 is not attacked in the process.

2 zeigt eine weitere schematische Schnittdarstellung des mikrotechnologischen Bauelements 100. In der Darstellung der 2 ist der in 1 gezeigte Teil des Bauelements 100 mit einem weiteren Teil des Bauelements 100 verbunden. Der weitere Teil des Bauelements 100 umfasst ein zweites Substrat 150 mit einer Oberseite 151. Bei dem zweiten Substrat 150 kann es sich beispielsweise ebenfalls um ein Siliziumsubstrat handeln. Die Oberseite 151 des zweiten Substrats 150 ist der Oberseite 111 des ersten Substrats 110 zugewandt. Auf der Oberseite 151 des zweiten Substrats 150 ist eine zweite Schicht 170 angeordnet. Die zweite Schicht 170 weist eine Oberseite 171 und eine Unterseite 172 auf. Die Unterseite 172 der zweiten Schicht 170 ist an der Oberseite 151 des zweiten Substrats 150 angeordnet. Die Oberseite 171 der zweiten Schicht 170 ist der Oberseite 131 der ersten Schicht 130 zugewandt. 2 shows a further schematic sectional view of the microtechnological component 100. In the representation of 2 is the in 1 part of the component 100 shown connected to a further part of the component 100 . The further part of the component 100 includes a second substrate 150 with a top 151. The second substrate 150 can also be a silicon substrate, for example. The top 151 of the second substrate 150 faces the top 111 of the first substrate 110 . A second layer 170 is arranged on the upper side 151 of the second substrate 150 . The second layer 170 has a top 171 and a bottom 172 . The bottom 172 of the second layer 170 is arranged on the top 151 of the second substrate 150 . The top 171 of the second layer 170 faces the top 131 of the first layer 130 .

Die zweite Schicht 170 besteht aus einem anderen oder dem gleichen Material wie die erste Schicht 130. Falls die erste Schicht 130 aus Aluminium oder aus mit Kupfer versetztem Aluminium (AICu) besteht, so kann die zweite Schicht 170 aus Germanium bestehen. Alternativ könnte die erste Schicht 130 aus Germanium und die zweite Schicht 170 aus Aluminium oder mit Kupfer versetztem Aluminium (AICu) bestehen.The second layer 170 consists of a different or the same material as the first layer 130. If the first layer 130 consists of aluminum or copper-laced aluminum (AICu), the second layer 170 can consist of germanium. Alternatively, the first layer 130 could be germanium and the second layer 170 aluminum or copper-laced aluminum (AICu).

Die erste Schicht 130 und die zweite Schicht 170 sind durch eine Bondverbindung 190 miteinander verbunden. Die laterale Abmessung der zweiten Schicht 170 parallel zu ihrer Oberseite 171 ist im dargestellten Beispiel geringer als die laterale Abmessung der ersten Schicht 130 in Richtung parallel zu ihrer Oberseite 131. Somit ist die Bondfläche 191 der eutektischen Bondverbindung 190 etwa so groß wie die Fläche der Oberseite 171 der zweiten Schicht 170.The first layer 130 and the second layer 170 are connected to one another by a bond connection 190 . In the example shown, the lateral dimension of the second layer 170 parallel to its top side 171 is less than the lateral dimension of the first layer 130 in the direction parallel to its top side 131. The bonding surface 191 of the eutectic bond connection 190 is therefore approximately as large as the surface of the top side 171 of the second layer 170.

Da die durch Randbereiche der ersten Schicht 130 gebildete erste Überdeckung 140 mit dem ersten Substrat 110 in Kontakt steht, kommt es im Bereich dieses Kontakts zwischen der ersten Überdeckung 140 und dem ersten Substrat 110 zu einer Interdiffusion 141 zwischen den Materialien des ersten Substrats 110 und der ersten Schicht 130. Durch eine geeignete Wahl der zum Herstellen der eutektischen Bondverbindung 190 verwendeten Bondtemperatur, des dabei verwendeten Temperaturprofils und der Bondzeit, sowie durch eine geeignete Wahl des Abstands zwischen dem Bereich der ersten Überdeckung 140 und der Bondfläche 191 ist es allerdings möglich, die Diffusion 141 des Materials des ersten Substrats 110 in das sich im Bereich der eutektischen Bondverbindung 190 bildende Eutektikum zu begrenzen.Since the first covering 140 formed by edge regions of the first layer 130 is in contact with the first substrate 110, there is an interdiffusion 141 between the materials of the first substrate 110 and the first substrate 110 in the area of this contact between the first covering 140 and the first substrate 110 first layer 130. By a suitable choice of the bonding temperature used to produce the eutectic bond connection 190, the temperature profile used and the bonding time used, and by a suitable choice of the distance between the area of the first covering 140 and the bonding surface 191, it is possible, however, to To limit diffusion 141 of the material of the first substrate 110 in the eutectic forming in the area of the eutectic bond connection 190 .

Falls das erste Substrat 110 aus Silizium besteht und die eutektische Bondverbindung 190 durch ein Aluminium-Germanium-Eutektikum gebildet wird, so bewirkt die Diffusion 141 von Silizium in das Eutektikum eine Erhöhung der Schmelztemperatur. Siliziumreiche Phasen erstarren dann bereits, während siliziumarme Phasen noch flüssig sind. Dieser Effekt kann dazu benutzt werden, ein laterales Verfließen des flüssigen Eutektikums zu beschränken. Da vor allem in den Randbereichen der ersten Schicht 130, also in den Bereichen der ersten Überdeckung 140 außerhalb der ersten Zwischenschicht 120, siliziumreiche Phasen zu finden sind, erstarrt hier das sich zwischen der ersten Schicht 130 und der zweiten Schicht 170 bildende Eutektikum zuerst und verhindert dadurch eine laterale Ausweitung der flüssigen Phasen.If the first substrate 110 consists of silicon and the eutectic bond connection 190 is formed by an aluminum-germanium eutectic, then the diffusion 141 of silicon into the eutectic causes an increase in the melting temperature. Silicon-rich phases then already solidify, while silicon-poor phases are still liquid. This effect can be used to limit lateral flow of the liquid eutectic. Since primarily in the edge areas of the first layer 130, ie in the areas of the first covering 140 outside of the first intermediate layer 120, silicon-rich phases can be found, the eutectic forming between the first layer 130 and the second layer 170 solidifies here first and thereby prevents a lateral expansion of the liquid phases.

Im folgenden werden weitere Ausführungsformen mikrotechnologischer Bauelemente erläutert. Dabei werden stets nur Komponenten beschrieben, die vom mikrotechnologischen Bauelement 100 der 1 und 2 abweichen.Further embodiments of microtechnology components are explained below. In this case, only components are always described that are from the microtechnological device 100 of 1 and 2 differ.

Gleiche und gleich wirkende Teile sind mit denselben Bezugszeichen wie in 1 und 2 versehen und werden nicht erneut detailliert beschrieben.Identical and identically functioning parts have the same reference numbers as in FIG 1 and 2 provided and will not be described again in detail.

3 zeigt eine schematische Schnittdarstellung eines mikrotechnologischen Bauelements 200 gemäß einer zweiten Ausführungsform. Das mikrotechnologische Bauelement 200 weist anstelle der zweiten Schicht 170 eine zweite Schicht 270 mit einer Oberseite 271 und einer Unterseite 272 auf. Zwischen der Unterseite 272 der zweiten Schicht 270 und der Oberseite 151 des zweiten Substrats 150 ist eine zweite Zwischenschicht 260 angeordnet. Die zweite Zwischenschicht 260 weist eine Oberseite 261 und eine Unterseite 262 auf. Die Unterseite 262 steht in Kontakt mit der Oberseite 151 des zweiten Substrats 150. Die Oberseite 261 steht in Kontakt mit der Unterseite 272 der zweiten Schicht 270. Seitenflächen 263 der zweiten Zwischenschicht 260 sind nicht bedeckt, sondern von au-ßen zugänglich. Die zweite Zwischenschicht 260 dient als Haftschicht zur Verbesserung der Haftung der zweiten Schicht 270 am zweiten Substrat 150. Außerdem dient die zweite Zwischenschicht 260 als Diffusionsbarriere zur Reduzierung oder Verhinderung einer Interdiffusion des Materials des zweiten Substrats 150 und des Materials der zweiten Schicht 270. Die zweite Zwischenschicht 260 und die zweite Schicht 270 können nacheinander auf die Oberseite 151 des zweiten Substrats 150 aufgebracht und gemeinsam unter Verwendung der gleichen Lackmaske strukturiert worden sein. 3 FIG. 1 shows a schematic sectional illustration of a microtechnical component 200 according to a second specific embodiment. Instead of the second layer 170 , the microtechnology component 200 has a second layer 270 with a top side 271 and a bottom side 272 . A second intermediate layer 260 is arranged between the underside 272 of the second layer 270 and the upper side 151 of the second substrate 150 . The second intermediate layer 260 has an upper side 261 and an underside 262 . The bottom 262 is in contact with the top 151 of the second substrate 150. The top 261 is in contact with the bottom 272 of the second layer 270. Side faces 263 of the second intermediate layer 260 are not covered but are accessible from the outside. The second intermediate layer 260 serves as an adhesion layer to improve the adhesion of the second layer 270 to the second substrate 150. The second intermediate layer 260 also serves as a diffusion barrier to reduce or prevent interdiffusion of the material of the second substrate 150 and the material of the second layer 270. The second Intermediate layer 260 and the second layer 270 can be applied successively to the upper side 151 of the second substrate 150 and patterned together using the same resist mask.

4 zeigt in schematischer Schnittdarstellung ein mikrotechnologisches Bauelement 300 gemäß einer dritten Ausführungsform. Beim mikrotechnologischen Bauelement 300 ist auf der Oberseite 151 des zweiten Substrats 150 eine zweite Zwischenschicht 360 mit einer Oberseite 361 und einer Unterseite 362 angeordnet. Die Unterseite 362 steht in Kontakt mit der Oberseite 151 des zweiten Substrats 150. Auf der Oberseite 361 der zweiten Zwischenschicht 360 ist eine zweite Schicht 370 mit einer Oberseite 371 und einer Unterseite 372 angeordnet. Die Unterseite 372 steht in Kontakt mit der Oberseite 361 der zweiten Zwischenschicht 360. Die Oberseite 371 der zweiten Schicht 370 bildet eine Bondverbindung 190 mit der ersten Schicht 130. 4 1 shows, in a schematic sectional illustration, a microtechnological component 300 according to a third specific embodiment. A second intermediate layer 360 with a top side 361 and a bottom side 362 is arranged on the top side 151 of the second substrate 150 in the case of the microtechnology component 300 . The bottom 362 is in contact with the top 151 of the second substrate 150. On the top 361 of the second intermediate layer 360, a second layer 370 with a top 371 and a bottom 372 is arranged. The bottom 372 is in contact with the top 361 of the second intermediate layer 360. The top 371 of the second layer 370 forms a bond connection 190 with the first layer 130.

Die laterale Ausdehnung der zweiten Schicht 370 ist größer als die laterale Ausdehnung der zweiten Zwischenschicht 360. Dadurch sind Randbereiche der zweiten Schicht 370 in Kontakt mit der Oberseite 151 des zweiten Substrats 150 und bilden eine zweite Überdeckung 380, die die Seitenflächen 363 der zweiten Zwischenschicht 360 überdeckt. Beim mikrotechnologischen Bauelement 300 sind die Seitenflächen 363 der zweiten Zwischenschicht 360 also ebenso geschützt wie die Seitenflächen 123 der ersten Zwischenschicht 120. Dies hat den Vorteil, dass auch die zweite Zwischenschicht 260 bei einem Ätzschritt nicht angegriffen werden kann und es dadurch auch nicht zu einer Unterätzung der zweiten Schicht 370 kommen kann.The lateral extent of the second layer 370 is greater than the lateral extent of the second intermediate layer 360. As a result, edge regions of the second layer 370 are in contact with the top side 151 of the second substrate 150 and form a second covering 380, which covers the side surfaces 363 of the second intermediate layer 360 covered. In the case of the microtechnical component 300, the side surfaces 363 of the second intermediate layer 360 are protected in the same way as the side surfaces 123 of the first intermediate layer 120. This has the advantage that the second intermediate layer 260 cannot be attacked during an etching step either, and as a result there is also no undercutting of the second layer 370 can come.

5 zeigt eine schematische Schnittdarstellung eines mikrotechnologischen Bauelements 400 gemäß einer vierten Ausführungsform. Das mikrotechnologische Bauelement 400 entspricht weitgehend dem mikrotechnologischen Bauelement 300 der 4, weist jedoch anstatt der zweiten Schicht 370 eine zweite Schicht 470 mit größerer lateraler Ausdehnung auf. Die zweite Schicht 470 weist wiederum eine der ersten Schicht 130 zugewandte Oberseite 471 und eine der zweiten Zwischenschicht 360 zugewandte Unterseite 472 auf. Da die laterale Ausdehnung der zweiten Schicht 470 wesentlich größer als die laterale Ausdehnung der zweiten Zwischenschicht 360 ist, ist der mit der Oberseite 151 des zweiten Substrats 150 in Kontakt stehende und eine zweite Überdeckung 480 bildende Teil der zweiten Schicht 470 beim mikrotechnologischen Bauelement 400 wesentlich größer als der die zweite Überdeckung 380 bildende Abschnitt der zweiten Schicht 370 des mikrotechnologischen Bauelements 300. Hierdurch ist beim mikrotechnologischen Bauelement 400 auch der Bereich einer Interdiffusion zwischen der zweiten Schicht 470 und dem zweiten Substrat 150 vergrößert. 5 FIG. 1 shows a schematic sectional illustration of a microtechnical component 400 according to a fourth specific embodiment. The microtechnology component 400 largely corresponds to the microtechnology component 300 of FIG 4 , however, instead of the second layer 370, it has a second layer 470 with a greater lateral extension. The second layer 470 in turn has a top side 471 facing the first layer 130 and a bottom side 472 facing the second intermediate layer 360 . Since the lateral extent of the second layer 470 is significantly larger than the lateral extent of the second intermediate layer 360, the part of the second layer 470 that is in contact with the top side 151 of the second substrate 150 and forms a second covering 480 is significantly larger in the microtechnology component 400 as the section of the second layer 370 of the microtechnology component 300 that forms the second covering 380. As a result, the region of an interdiffusion between the second layer 470 and the second substrate 150 is also enlarged in the microtechnology component 400.

6 zeigt in schematischer Schnittdarstellung ein mikrotechnologisches Bauelement 500 gemäß einer fünften Ausführungsform. Das mikrotechnologische Bauelement 500 weist im Unterschied zum mikrotechnologischen Bauelement 100 anstelle der ersten Schicht 130 eine erste Schicht 530 mit einer Oberseite 531 und einer Unterseite 532 auf. Die Unterseite 532 der ersten Schicht 530 ist auf der Oberseite 121 der ersten Zwischenschicht 120 angeordnet. Die laterale Ausdehnung der ersten Schicht 530 entspricht der lateralen Ausdehnung der ersten Zwischenschicht 120. Die erste Schicht 530 und die erste Zwischenschicht 120 können in einem gemeinsamen Verfahrensschritt unter Verwendung derselben Lackmaske strukturiert worden sein. 6 1 shows a schematic sectional illustration of a microtechnology component 500 according to a fifth specific embodiment. In contrast to the microtechnology component 100 , the microtechnology component 500 has a first layer 530 with a top side 531 and a bottom side 532 instead of the first layer 130 . The bottom 532 of the first layer 530 is arranged on the top 121 of the first intermediate layer 120 . The lateral extent of the first layer 530 corresponds to the lateral extent of the first intermediate layer 120. The first layer 530 and the first intermediate layer 120 can have been structured in a common method step using the same resist mask.

Die Oberseite 531 der ersten Schicht 530 sowie die Seitenflächen 123 der ersten Zwischenschicht 120 und auch die Seitenflächen der ersten Schicht 530 sind durch eine erste Überdeckung 540 überdeckt. Die erste Überdeckung 540 kann aus demselben Material wie die erste Schicht 530 bestehen. Bevorzugt besteht die erste Überdeckung 540 jedoch aus einem anderen Material als die erste Schicht 530, besonders bevorzugt aus demselben Material wie die zweite Schicht 170. Beispielsweise kann die erste Schicht 530 aus Aluminium oder aus mit Kupfer versetztem Aluminium (AICu) bestehen. Die zweite Schicht 170 und die erste Überdeckung 540 bestehen dann aus Germanium.The top 531 of the first layer 530 and the side surfaces 123 of the first intermediate layer 120 and also the side surfaces of the first layer 530 are covered by a first covering 540 . The first overlay 540 can be made of the same material as the first layer 530 . Preferably, however, the first overlay 540 is made of a different material than the first layer 530, more preferably the same material as the second layer 170. For example, the first layer 530 may be made of aluminum or copper-laced aluminum (AICu). The second layer 170 and the first overlay 540 then consist of germanium.

Die erste Überdeckung 540 weist eine Überdeckungsdicke 541 auf, die wesentlich geringer als eine Dicke 173 der zweiten Schicht 170 und auch geringer als eine Dicke 533 der ersten Schicht 530 ist. Die erste Überdeckung 540 kann in einem der Strukturierung der ersten Zwischenschicht 120 und der ersten Schicht 530 nachfolgenden Prozessschritt aufgebracht worden sein. Die erste Überdeckung 540 bildet eine funktionale Ätzbarriere, die die Seitenflächen 523 der ersten Zwischenschicht 120 während eines Ätzschritts, beispielsweise eines HF-Gasphasenätzschritts, schützt.The first overlay 540 has an overlay thickness 541 that is substantially less than a thickness 173 of the second layer 170 and also less than a thickness 533 of the first layer 530 . The first covering 540 may have been applied in a process step subsequent to the structuring of the first intermediate layer 120 and the first layer 530 . The first cladding 540 forms a functional etch barrier that protects the side surfaces 523 of the first intermediate layer 120 during an etch step, for example an HF gas phase etch step.

Ein Vorteil der Überdeckung der ersten Schicht 530 durch die erste Überdeckung 540 aus dem Material der zweiten Schicht 170 besteht darin, dass es durch den Kontakt zwischen der ersten Überdeckung 540 und der Oberseite 531 der ersten Schicht 530 bereits zu einer definierten Ausbildung einer eutektischen Schmelze kommt, bevor die erste Schicht 530 und die erste Überdeckung 540 in Kontakt mit der zweiten Schicht 170 gebracht werden. Hierdurch können kleine Unebenheiten und durch Kratzer oder Verschmutzungen verursachte Defekte ausgeglichen werden.One advantage of covering the first layer 530 with the first covering 540 made from the material of the second layer 170 is that the contact between the first covering 540 and the upper side 531 of the first layer 530 already results in a defined formation of a eutectic melt , before the first layer 530 and the first overlay 540 are brought into contact with the second layer 170. FIG. This allows small bumps and defects caused by scratches or dirt to be compensated.

7 zeigt in schematischer Schnittdarstellung ein mikrotechnologisches Bauelement 600 gemäß einer sechsten Ausführungsform. Gegenüber dem mikrotechnologischen Bauelement 500 ist beim mikrotechnologischen Bauelement 600 statt der ersten Überdeckung 540 eine erste Überdeckung 640 vorhanden. Auch die erste Überdeckung 640 besteht bevorzugt aus einem anderen Material als die erste Schicht 530, besonders bevorzugt aus dem Material der zweiten Schicht 170. Im Unterschied zur ersten Überdeckung 540 überdeckt die erste Überdeckung 640 des mikrotechnologischen Bauelements 600 jedoch nur die Seitenflächen der ersten Schicht 530 und die Seitenflächen 123 der ersten Zwischenschicht 120, nicht jedoch die Oberseite 531 der ersten Schicht 530. Ein auf der Oberseite 531 der ersten Schicht 530 angelagerter Teil der ersten Überdeckung 640 kann beispielsweise während einer nachfolgenden Strukturierung entfernt worden sein. Das mikrotechnologische Bauelement 600 bietet den Vorteil, dass sich eine eutektische Bondverbindung direkt zwischen der ersten Schicht 530 und der zweiten Schicht 170 ausbilden kann. 7 1 shows, in a schematic sectional illustration, a microtechnology component 600 according to a sixth specific embodiment. Compared to the microtechnology component 500 , the microtechnology component 600 has a first covering 640 instead of the first covering 540 . The first covering 640 also preferably consists of a different material than the first layer 530, particularly preferably from the material of the second layer 170. In contrast to the first covering 540, however, the first covering 640 of the microtechnical component 600 covers only the side surfaces of the first layer 530 and the side faces 123 of the first intermediate layer 120, but not the top side 531 of the first layer 530. A part of the first covering 640 deposited on the top side 531 of the first layer 530 may have been removed during subsequent structuring, for example. The microtechnology component 600 offers the advantage that a eutectic bond connection can form directly between the first layer 530 and the second layer 170 .

8 zeigt in schematischer Schnittdarstellung ein mikrotechnologisches Bauelement 700 gemäß einer siebten Ausführungsform. Im Unterschied zum mikrotechnologischen Bauelement 100 weist das mikrotechnologische Bauelement 700 statt des zweiten Substrats 150 ein zweites Substrat 750 mit einer Oberseite 751 auf. Die Oberseite 751 ist der Oberseite 111 des ersten Substrats 110 zugewandt. Das zweite Substrat 750 besteht aus Silizium. Die erste Schicht 130 auf dem ersten Substrat 110 besteht bei dem mikrotechnologischen Bauelement 700 aus Gold. Auf der Oberseite 751 des zweiten Substrats 750 sind weder eine zweite Zwischenschicht noch eine zweite Schicht angeordnet. Stattdessen steht die Oberseite 751 des zweiten Substrat 750 in direktem Kontakt mit der Oberseite 131 der ersten Schicht 130. Zwischen der ersten Schicht 130 und dem zweiten Substrat 150 ist eine eutektische Bondverbindung aus einem Gold-Silizium-Eutektikum ausgebildet. 8th FIG. 12 shows a microtechnology component 700 according to a seventh embodiment in a schematic sectional illustration. In contrast to the microtechnology component 100 , the microtechnology component 700 has a second substrate 750 with a top side 751 instead of the second substrate 150 . The top 751 faces the top 111 of the first substrate 110 . The second substrate 750 is made of silicon. In the case of the microtechnology component 700, the first layer 130 on the first substrate 110 consists of gold. Neither a second intermediate layer nor a second layer are arranged on the upper side 751 of the second substrate 750 . Instead, the upper side 751 of the second substrate 750 is in direct contact with the upper side 131 of the first layer 130. A eutectic bond connection made of a gold-silicon eutectic is formed between the first layer 130 and the second substrate 150. FIG.

Bei einer weiteren Ausführungsform kann das AI oder das AICu in den 1 bis 7 durch Au ersetzt und eine eutektische Verbindung zwischen Au und Ge realisiert werden.In another embodiment, the Al or the AlCu in the 1 until 7 replaced by Au and a eutectic connection between Au and Ge can be realized.

Werden die oben beschriebenen Ausführungsformen der 1 bis 6 in Kombination mit einem Transient-Liquid-Phase (TLP) Bond genutzt, muss eine erste Schicht (130,530) in der Ausführung einer Mehrfachschicht bestehend aus z.B. Kupfer/Zinn, Kupfer/Zinn/Indium, Gold/Indium gewählt werden. Dabei wird in einem bevorzugten Aufbau der Mehrfachschicht Kupfer (für Cu/Sn und Cu/Sn/In) bzw. Gold (für Au/In) auf die Oberseite (111) des Substrates (110) aufgebracht. In einem nächsten Schritt wird dann Zinn bzw. Indium auf das Kupfer bzw. Gold abgeschieden. Für das Dreifach-Materialsystem besteht die oberste Schicht aus Indium.If the embodiments described above 1 until 6 used in combination with a transient liquid phase (TLP) bond, a first layer (130,530) in the form of a multilayer consisting of eg copper/tin, copper/tin/indium, gold/indium must be selected. In a preferred structure of the multiple layer, copper (for Cu/Sn and Cu/Sn/In) or gold (for Au/In) is applied to the upper side (111) of the substrate (110). In a next step, tin or indium is then deposited on the copper or gold. For the triple material system, the top layer is indium.

Eine zweite Schicht (170) auf einem zweiten Substrat (150) wäre entsprechend aus Kupfer, Kupfer/Gold oder Gold zu wählen. In dem Fall der Kupfer/Gold Doppelschicht, wird Kupfer zunächst auf die Oberfläche (151) des zweiten Substrates (150) deponiert und danach mit Gold bedeckt.A second layer (170) on a second substrate (150) would have to be chosen from copper, copper/gold or gold accordingly. In the case of the copper/gold bilayer, copper is first deposited onto the surface (151) of the second substrate (150) and then covered with gold.

Im Falle der Mehrfachschichten kann die obere Schicht die Rolle der Überdeckung (140) übernehmen.In the case of multiple layers, the upper layer can play the role of cover (140).

Claims (12)

Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600, 700) mit einem ersten Substrat (110), wobei auf dem ersten Substrat (110) eine erste Schicht (130, 530) angeordnet ist, wobei zwischen dem ersten Substrat (110) und der ersten Schicht (130, 530) eine erste Zwischenschicht (120) angeordnet ist, wobei Seitenflächen (123) der ersten Zwischenschicht (120) durch eine Überdeckung (140, 540, 640) überdeckt sind, wobei zwischen der ersten Schicht (130, 530) und einer weiteren Schicht (370, 470) eine Bondverbindung (190) besteht, wobei die weitere Schicht (370, 470) eine auf einem zweiten Substrat (150) angeordnete zweite Schicht (370, 470) ist, wobei die erste Schicht (130, 530) und die zweite Schicht (370, 470) unterschiedliche Materialien aufweisen, wobei zwischen dem zweiten Substrat (150) und der zweiten Schicht (370, 470) eine zweite Zwischenschicht (360) angeordnet ist, wobei eine laterale Ausdehnung der zweiten Schicht (370, 470) größer als eine laterale Ausdehnung der zweiten Zwischenschicht (360) ist, wobei Randbereiche der zweiten Schicht (370, 470) eine zweite Überdeckung (380) bilden, die Seitenflächen (363) der zweiten Zwischenschicht (360) überdeckt.Microtechnology component (100, 200, 300, 400, 500, 600, 700) with a first substrate (110), a first layer (130, 530) being arranged on the first substrate (110), a first intermediate layer (120) being arranged between the first substrate (110) and the first layer (130, 530), wherein side surfaces (123) of the first intermediate layer (120) are covered by a covering (140, 540, 640), there being a bonding connection (190) between the first layer (130, 530) and a further layer (370, 470), wherein the further layer (370, 470) is a second layer (370, 470) arranged on a second substrate (150), wherein the first layer (130, 530) and the second layer (370, 470) have different materials, a second intermediate layer (360) being arranged between the second substrate (150) and the second layer (370, 470), wherein a lateral extent of the second layer (370, 470) is greater than a lateral extent of the second intermediate layer (360), edge regions of the second layer (370, 470) forming a second covering (380) which covers side surfaces (363) of the second intermediate layer (360). Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600, 700) nach Anspruch 1, wobei die erste Schicht (130, 530) und die Überdeckung (140, 540, 640) Aluminium, mit Kupfer versetztes Aluminium (AICu), Kupfer, Gold oder Germanium aufweisen.Microtechnological component (100, 200, 300, 400, 500, 600, 700) according to claim 1 wherein the first layer (130, 530) and the overlay (140, 540, 640) comprise aluminum, copper-laced aluminum (AICu), copper, gold or germanium. Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600) nach Anspruch 1, wobei die erste Schicht (130, 530) als mehrlagige Schicht ausgebildet ist, die Kupfer und Zinn, Kupfer, Zinn und Indium oder Gold und Indium aufweist.Microtechnological component (100, 200, 300, 400, 500, 600) according to claim 1 , wherein the first layer (130, 530) is formed as a multilayer comprising copper and tin, copper, tin and indium, or gold and indium. Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600) nach einem der vorhergehenden Ansprüche, wobei die zweite Schicht (170, 270, 370, 470) Aluminium, mit Kupfer versetztes Aluminium (AICu), Germanium, Kupfer, Kupfer/Gold oder Gold aufweist.Microtechnological component (100, 200, 300, 400, 500, 600) according to any one of the preceding claims, wherein the second layer (170, 270, 370, 470) aluminium, aluminum mixed with copper (AICu), germanium, copper, copper/ has gold or gold. Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600) nach einem der Ansprüche 1 bis 3, wobei die zweite Schicht (170, 270, 370, 470) als mehrlagige Schicht ausgebildet ist, die Kupfer und Zinn, Kupfer, Zinn und Indium oder Gold und Indium aufweist.Microtechnological component (100, 200, 300, 400, 500, 600) according to one of Claims 1 until 3 , wherein the second layer (170, 270, 370, 470) is formed as a multi-layer layer comprising copper and tin, copper, tin and indium or gold and indium. Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600) nach einem der vorhergehenden Ansprüche, wobei die zweite Zwischenschicht (260, 360) Siliziumdioxid, Titan, Titannitrid, Tantal, Chrom oder Titanwolfram aufweist.Microtechnological component (100, 200, 300, 400, 500, 600) according to one of the preceding claims, wherein the second intermediate layer (260, 360) has silicon dioxide, titanium, titanium nitride, tantalum, chromium or titanium tungsten. Mikrotechnologisches Bauelement (500, 600) nach einem der vorhergehenden Ansprüche, wobei die Überdeckung (540, 640) durch eine dritte Schicht (540, 640) gebildet wird, wobei die erste Schicht (530) und die dritte Schicht (540, 640) unterschiedliche Materialien aufweisen.Microtechnological component (500, 600) according to one of the preceding claims, wherein the cover (540, 640) is formed by a third layer (540, 640), wherein the first layer (530) and the third layer (540, 640) have different materials. Mikrotechnologisches Bauelement (500, 600) nach Anspruch 7, wobei die dritte Schicht (540, 640) Silizium oder Germanium aufweist.Microtechnological component (500, 600) after claim 7 , wherein the third layer (540, 640) comprises silicon or germanium. Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600, 700) nach einem der vorhergehenden Ansprüche, wobei die erste Zwischenschicht (120) Siliziumdioxid, Titan, Titannitrid, Tantal, Chrom oder Titanwolfram aufweist.Microtechnological component (100, 200, 300, 400, 500, 600, 700) according to one of the preceding claims, wherein the first intermediate layer (120) has silicon dioxide, titanium, titanium nitride, tantalum, chromium or titanium tungsten. Mikrotechnologisches Bauelement (100, 200, 300, 400, 500, 600, 700) nach einem der vorhergehenden Ansprüche, wobei das Bauelement (100, 200, 300, 400, 500, 600, 700) ein mikromechanischer Sensor ist.Microtechnological component (100, 200, 300, 400, 500, 600, 700) according to one of the preceding claims, wherein the component (100, 200, 300, 400, 500, 600, 700) is a micromechanical sensor. Verfahren zum Herstellen eines mikrotechnologischen Bauelements (100, 200, 300, 400, 500, 600, 700) mit folgenden Schritten: - Bereitstellen eines Substrats (110); - Aufbringen einer Zwischenschicht (120) auf dem Substrat (110); - Aufbringen einer Schicht (130, 530) auf der Zwischenschicht (120); - Überdecken von Seitenflächen (123) der Zwischenschicht (120) mit einer Überdeckung (140, 540, 640); - Bonden der Schicht (130, 530) an eine weitere Schicht (170, 270, 370, 470, 750) , wobei die weitere Schicht (370, 470) eine auf einem zweiten Substrat (150) angeordnete zweite Schicht (370, 470) ist, wobei die erste Schicht (130, 530) und die zweite Schicht (370, 470) unterschiedliche Materialien aufweisen, wobei zwischen dem zweiten Substrat (150) und der zweiten Schicht (370, 470) eine zweite Zwischenschicht (360) angeordnet ist, wobei eine laterale Ausdehnung der zweiten Schicht (370, 470) größer als eine laterale Ausdehnung der zweiten Zwischenschicht (360) ist, wobei Randbereiche der zweiten Schicht (370, 470) eine zweite Überdeckung (380) bilden, die Seitenflächen (363) der zweiten Zwischenschicht (360) überdeckt.Method for producing a microtechnology component (100, 200, 300, 400, 500, 600, 700) with the following steps: - providing a substrate (110); - Application of an intermediate layer (120) on the substrate (110); - applying a layer (130, 530) on the intermediate layer (120); - covering side surfaces (123) of the intermediate layer (120) with a covering (140, 540, 640); - Bonding the layer (130, 530) to a further layer (170, 270, 370, 470, 750), the further layer (370, 470) being a second layer (370, 470) arranged on a second substrate (150) is, wherein the first layer (130, 530) and the second layer (370, 470) have different materials, a second intermediate layer (360) being arranged between the second substrate (150) and the second layer (370, 470), wherein a lateral extent of the second layer (370, 470) is greater than a lateral extent of the second intermediate layer (360), edge regions of the second layer (370, 470) forming a second covering (380) which covers side surfaces (363) of the second intermediate layer (360). Verfahren gemäß Anspruch 11, wobei zwischen dem Überdecken der Seitenkanten (123) und dem Bonden ein Ätzprozess durchgeführt wird.procedure according to claim 11 , wherein an etching process is performed between the covering of the side edges (123) and the bonding.
DE102012219622.6A 2012-10-26 2012-10-26 Micro-technological component with bonded connection Active DE102012219622B4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102012219622.6A DE102012219622B4 (en) 2012-10-26 2012-10-26 Micro-technological component with bonded connection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102012219622.6A DE102012219622B4 (en) 2012-10-26 2012-10-26 Micro-technological component with bonded connection

Publications (2)

Publication Number Publication Date
DE102012219622A1 DE102012219622A1 (en) 2014-04-30
DE102012219622B4 true DE102012219622B4 (en) 2022-06-30

Family

ID=50479629

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102012219622.6A Active DE102012219622B4 (en) 2012-10-26 2012-10-26 Micro-technological component with bonded connection

Country Status (1)

Country Link
DE (1) DE102012219622B4 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3083467A1 (en) * 2018-07-05 2020-01-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR SEALING PARTS BETWEEN THEM WITH AN EUTECTIC ALLOY BASED ON ALUMINUM
CN111146170A (en) * 2019-12-30 2020-05-12 颀中科技(苏州)有限公司 Packaging structure and forming method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146353A1 (en) 2001-09-20 2003-04-30 Advanced Micro Devices Inc A solder bump structure and a method of making the same
DE102007023590A1 (en) 2007-05-21 2008-11-27 Epcos Ag Component with mechanically loadable connection surface
EP2262008A2 (en) 2002-01-28 2010-12-15 Nichia Corporation Nitride semiconductor element with supporting substrate and method for producing nitride semiconductor element
US20110024923A1 (en) 2005-08-26 2011-02-03 Innovative Micro Technology Wafer level hermetic bond using metal alloy with keeper layer
EP2331455B1 (en) 2008-09-26 2012-07-11 Robert Bosch GmbH Contact arrangement for establishing a spaced, electrically conducting connection between microstructured components

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146353A1 (en) 2001-09-20 2003-04-30 Advanced Micro Devices Inc A solder bump structure and a method of making the same
EP2262008A2 (en) 2002-01-28 2010-12-15 Nichia Corporation Nitride semiconductor element with supporting substrate and method for producing nitride semiconductor element
US20110024923A1 (en) 2005-08-26 2011-02-03 Innovative Micro Technology Wafer level hermetic bond using metal alloy with keeper layer
DE102007023590A1 (en) 2007-05-21 2008-11-27 Epcos Ag Component with mechanically loadable connection surface
EP2331455B1 (en) 2008-09-26 2012-07-11 Robert Bosch GmbH Contact arrangement for establishing a spaced, electrically conducting connection between microstructured components

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
G. Mordi, et al. "Low-κ organic layer as a top gate dielectric for graphene field effect transistors." Applied Physics Letters 100.19, 2012, 193117-1 – 3

Also Published As

Publication number Publication date
DE102012219622A1 (en) 2014-04-30

Similar Documents

Publication Publication Date Title
EP1945563B1 (en) Component that can be inserted using microsystems technology, and soldering method for connecting corresponding wafer or component parts
DE112012004162B4 (en) Binding process for wafers and structure of the binding site
EP2499085B1 (en) Micromechanical method and corresponding assembly for bonding semiconductor substrates and correspondingly bonded semiconductor chip
DE102012206869A1 (en) Micromechanical component and method for producing a micromechanical component
WO2009049958A2 (en) Composite comprising at least two semiconductor substrates and production method
DE102014221620B4 (en) Semiconductor device
DE3028044C1 (en) Solderable layer system
EP2438005B1 (en) Micromechanical component having eutectic bond between two substrates and method for producing such a micromechanical component
DE102012213566A1 (en) Method for producing a bonding pad for thermocompression bonding and bonding pad
DE102012219622B4 (en) Micro-technological component with bonded connection
WO2006092200A1 (en) Weldable contact and method for the production thereof
DE19817311A1 (en) Manufacture of micromechanical component, such as rotation rate sensor
WO2010066494A2 (en) Arrangement of two substrates having a slid bond and method for producing such an arrangement
WO2010054875A1 (en) Arrangement of at least two wafers with a bonding connection and method for producing such an arrangement
EP2287899B1 (en) Solder connection with a multilayered solderable layer and corresponding manufacturing method
DE102014210852B4 (en) Component with two semiconductor components which are connected to one another via a structured bonding connection layer and method for producing such a component
DE102019209065B4 (en) Semiconductor device and method for producing the semiconductor device
EP1111671B1 (en) Process for fabricating a semiconductor device
DE102014216746A1 (en) WAFER LEVEL PACKAGE OF A MEMS SENSOR AND METHOD FOR MANUFACTURING THEREOF
WO2020099127A1 (en) Method for producing a microelectromechanical sensor and microelectromechanical sensor
DE4437963C2 (en) Multilayer printed circuit board and process for its manufacture
WO2012152307A1 (en) Component carrier assembly having a trench structure which separates component carrier regions, and method for producing a plurality of component carrier regions
DE102007023590A1 (en) Component with mechanically loadable connection surface
DE19528441A1 (en) Under metallization for solder materials
DE102019212881A1 (en) Process for laser micro welding of two components and a composite component

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R016 Response to examination communication
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R020 Patent grant now final