DE102010004230A1 - Integrated circuit for use in e.g. electronic system, has interface-structures directly connected to doped area in respective partial areas of contact surface, where structures are made from respective conducting materials - Google Patents
Integrated circuit for use in e.g. electronic system, has interface-structures directly connected to doped area in respective partial areas of contact surface, where structures are made from respective conducting materials Download PDFInfo
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- DE102010004230A1 DE102010004230A1 DE102010004230A DE102010004230A DE102010004230A1 DE 102010004230 A1 DE102010004230 A1 DE 102010004230A1 DE 102010004230 A DE102010004230 A DE 102010004230A DE 102010004230 A DE102010004230 A DE 102010004230A DE 102010004230 A1 DE102010004230 A1 DE 102010004230A1
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- integrated circuit
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- 239000004020 conductor Substances 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 claims abstract description 122
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 23
- 239000010937 tungsten Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- -1 tungsten nitride Chemical class 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 5
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 142
- 230000004888 barrier function Effects 0.000 claims description 31
- 238000002161 passivation Methods 0.000 claims description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- 239000002243 precursor Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 239000002245 particle Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 230000005670 electromagnetic radiation Effects 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims description 2
- 239000002075 main ingredient Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 64
- 230000006870 function Effects 0.000 description 58
- 239000011229 interlayer Substances 0.000 description 14
- 239000000945 filler Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000012212 insulator Substances 0.000 description 7
- 229910021332 silicide Inorganic materials 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910052798 chalcogen Inorganic materials 0.000 description 3
- 150000001787 chalcogens Chemical class 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002736 metal compounds Chemical class 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052711 selenium Inorganic materials 0.000 description 2
- 239000011669 selenium Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- 239000011593 sulfur Substances 0.000 description 2
- 229910052714 tellurium Inorganic materials 0.000 description 2
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 2
- BUHVIAUBTBOHAG-FOYDDCNASA-N (2r,3r,4s,5r)-2-[6-[[2-(3,5-dimethoxyphenyl)-2-(2-methylphenyl)ethyl]amino]purin-9-yl]-5-(hydroxymethyl)oxolane-3,4-diol Chemical compound COC1=CC(OC)=CC(C(CNC=2C=3N=CN(C=3N=CN=2)[C@H]2[C@@H]([C@H](O)[C@@H](CO)O2)O)C=2C(=CC=CC=2)C)=C1 BUHVIAUBTBOHAG-FOYDDCNASA-N 0.000 description 1
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- 229910019974 CrSi Inorganic materials 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910021140 PdSi Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910019847 RhSi Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910006249 ZrSi Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
In der Halbleitertechnologie beeinflusst der Kontaktwiderstand zwischen einem halbleitenden Gebiet einerseits und einer leitenden Struktur andererseits u. a. die Schaltgeschwindigkeit und die elektrischen Verluste eines integrierten Schaltkreises. Bei einem ohmschen Kontakt zwischen einem halbleitenden Gebiet und einer leitenden Struktur reduziert eine ausreichend hohe Dotierung des halbleitenden Gebiets nahe an der Kontaktfläche zur leitenden Struktur die Weite der Verarmungszone an der Kontaktfläche derart, dass Ladungsträger durch die Potentialbarriere zu tunneln vermögen. Der Kontaktwiderstand einer solchen Struktur hängt exponentiell von der Barrierenhöhe ab.In Semiconductor technology influences the contact resistance between a semiconducting field on the one hand and a conductive structure on the other on the other hand u. a. the switching speed and the electrical Losses of an integrated circuit. With an ohmic contact between a semiconducting area and a conductive structure reduces a sufficiently high doping of the semiconductive region close to the contact surface to the conductive structure the width the depletion zone at the contact surface such that charge carriers to tunnel through the potential barrier. The contact resistance such a structure depends exponentially on the barrier height from.
Gemäß einem
in der
Gemäß einem
in der
Die
Die
Veröffentlichung
Es besteht ein Bedürfnis nach einem einfachen Integrationsschema mit an n-halbleitende und p-halbleitende Gebiete angepassten Kontaktstrukturen.It there is a need for a simple integration scheme with contact structures adapted to n-semiconducting and p-semiconducting regions.
Ausführungsformen und Vorteile der Erfindung werden anhand der nachfolgenden Figuren dargestellt und beschrieben. Der Schwerpunkt der Ausführungen liegt dabei auf der Darstellung der der Erfindung zugrunde liegenden Prinzipien. Die Darstellung der einzelnen Elemente und Teilstrukturen erfolgt nicht notwendigerweise maßstäblich. Die den unterschiedlichen Ausführungsformen zugeordneten Merkmale verschiedener Ausführungsformen können miteinander kombiniert werden, sofern sie sich nicht ausschließen.embodiments and advantages of the invention will be apparent from the following figures and described. The focus of the designs lies doing so on the representation of the principles underlying the invention. The representation of the individual elements and substructures takes place not necessarily to scale. The different ones Embodiments associated with various embodiments embodiments can be combined with each other, if they are not exclude.
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Auf
einer Hauptfläche
Eine
erste und eine zweite Kontaktstruktur
Beiden
Kontaktstrukturen
Der
Kontaktwiderstand hängt exponentiell von der Barrierenhöhe
zwischen der Kontaktstruktur und dem jeweils kontaktierten dotierten
Gebiet ab. Die Barrierenhöhen ϕBn, ϕBp für n- und p-dotierte Gebiete
ergeben sich aus der Austrittsarbeit ϕm des Kontaktmaterials,
der Elektronenaffinität χ, dem Bandabstand Eg und dem Ladungsneutralitätsniveau ECNL des Halbleitermaterials sowie einem Interface-Index
S näherungsweise nach den Gleichungen (1) und (2):
In beiden Fällen ergibt sich die Barrierenhöhe aus der Summe aus einem ersten, von der Austrittsarbeit ϕm des Kontaktmaterials abhängigen Term und aus einem zweiten, von der Austrittsarbeit ϕm unabhängigen Term. Der erste Term ergibt sich aus der Annahme, dass der Energieabstand zum Vakuumniveau am Interface zwischen dotiertem Gebiet und Kontaktstruktur unverändert bleibt. Der zweite Term berücksichtigt die Wirkung von Oberflächenzuständen (interface states, surface states), die am Interface das Fermi-Niveau im Kontaktmaterial mehr oder weniger stark auf ein Ladungsneutralitätsniveau zwischen dem Leitungsbandniveau und dem Valenzbandniveaus zwingen (”pinnen”). Der Interface-Index S gibt die Stärke des „Pinnens” an. Für S = 0 ist das Fermi-Niveau im Metall auf das Ladungsneutralitätsniveau im Halbleiter eingerastet („gepinnt”) und die Barrierenhöhen ϕBn, ϕBp sind unabhängig von der Austrittsarbeit des Kontaktmaterials. Für S = 1 sind die Barrierenhöhen ϕBn, ϕBp ausschließlich von der Elektronenaffinität und der Bandlücke des Halbleitermaterials sowie der Austrittsarbeit des Kontaktmaterials abhängig. Der Interface-Index S ist abhängig von der chemisch/physikalischen Beschaffenheit der Oberflächen am Interface.In both cases, the barrier height results from the sum of a first term dependent on the work function φ m of the contact material and a second term independent of the work function φ m . The first term results from the assumption that the energy gap is at the vacuum level remains unchanged at the interface between doped region and contact structure. The second term takes into account the effect of interface states, surface states, which at the interface more or less force the Fermi level in the contact material to a level of charge neutrality between conduction band level and valence band levels ("pinning"). The interface index S indicates the strength of "pinning". For S = 0, the Fermi level in the metal is pinned to the charge neutral level in the semiconductor and the barrier heights φ Bn , φ Bp are independent of the work function of the contact material. For S = 1, the barrier heights φ Bn , φ Bp are exclusively dependent on the electron affinity and the band gap of the semiconductor material as well as the work function of the contact material. The interface index S depends on the chemical / physical nature of the surfaces on the interface.
Gemäß einer
Ausführungsform werden das erste und das zweite leitfähige
Material so gewählt, dass sowohl eine erste Barrierenhöhe ϕBn nach der Gleichung (1) zwischen dem n-dotierten
Gebiet
Gemäß einer weiteren Ausführungsform ist die erste Austrittsarbeit kleiner der um etwa 15% des Bandabstands erhöhten Elektronenaffinität im Halbleitermaterial. Beispielsweise ist die erste Austrittsarbeit kleiner als die Elektronenaffinität bzw. überschreitet diese um nicht mehr als 10% des Bandabstands. Damit kann der erste Term in der Gleichung (1) minimiert werden.According to one Another embodiment is the first work function less than about 15% of the band gap increased electron affinity in the semiconductor material. For example, the first work function less than the electron affinity or exceeds these by no more than 10% of the band gap. This can be the first Term in equation (1) are minimized.
Wird, beispielsweise durch Ausbilden einer Passivierungsschicht, das Interface ohne oder mit wenig Oberflächenzuständen gebildet, so dass der erste Term der Gleichung (1) zu einem maßgeblichen Anteil von z. B. mindestens 10% die Barrierenhöhe bestimmt, dann kann das erste leitfähige Material auch so gewählt werden, dass die erste Austrittsarbeit näherungsweise an die Elektronenaffinität angepasst ist oder gleich der Elektronenaffinität ist. Dabei kann die erste Austrittsarbeit zum Beispiel vom Mengenverhältnis zwischen Hauptbestandteilen des ersten Materials abhängen, so dass die tatsächliche Austrittsarbeit im Rahmen fertigungsbedingter Toleranzen von einem vorgegebenen Wert, z. B. der Elektronenaffinität, abweichen kann.Becomes, for example, by forming a passivation layer, the interface formed with little or no surface states, so that the first term of equation (1) becomes a significant proportion from Z. B. at least 10% determines the barrier height, then The first conductive material may also be chosen Be that approximate to the first work function the electron affinity is matched or equal to the electron affinity is. In this case, the first work function, for example, the quantity ratio depend on main components of the first material, so that the actual work function under production Tolerances of a predetermined value, eg. B. the electron affinity, may differ.
Gemäß einer weiteren Ausführungsform kann das Interface, etwa durch Zugabe eines Chalkogens vollständig oder nahezu vollständig passiviert und das erste leitfähige Material so gewählt werden, dass die erste Austrittsarbeit kleiner der Elektronenaffinität ist, so dass über den ersten Term der Gleichung (1) der zweite Term mindestens teilweise kompensiert werden kann.According to one another embodiment, the interface, such as through Addition of a chalcogen completely or almost completely passivated and the first conductive material chosen be that the first work function is smaller than the electron affinity is such that over the first term of equation (1) the second term can be at least partially compensated.
Gemäß einer Ausführungsform ist die zweite Austrittsarbeit größer der um etwa 15% des Bandabstands reduzierten Summe aus Elektronenaffinität und Bandabstand im Halbleitermaterial. Beispielsweise ist die zweite Austrittsarbeit größer als die Summe bzw. unterschreitet diese um nicht mehr als 10% des Bandabstands. Auf diese Weise wird der erste Term in der Gleichung (2) minimiert.According to one Embodiment, the second work function is larger the sum of electron affinity reduced by about 15% of the band gap Band gap in the semiconductor material. For example, the second one Work function greater than the sum or below these by no more than 10% of the band gap. This way will the first term in equation (2) is minimized.
Wird das Interface ohne oder mit wenig Oberflächenzuständen gebildet, so dass der erste Term der Gleichung (2) die Barrierenhöhe zu einem maßgeblichen Anteil von z. B. mindestens 10% bestimmt, dann wird das zweite leitfähige Material so gewählt, dass die zweite Austrittsarbeit näherungsweise der Summe aus der Elektronenaffinität und dem Bandabstand entspricht oder gleich der Summe ist. Wie auch die erste Austrittsarbeit, kann auch die zweite Austrittsarbeit etwa vom Mengenverhältnis von Hauptbestandteilen des zweiten leitfähigen Materials zueinander abhängen, so dass die tatsächliche Austrittsarbeit im Rahmen fertigungsbedingter Toleranzen von einem vorgegebenen Wert, z. B. der Summe von Elektronenaffinität und Bandabstand, abweichen kann.If the interface is formed without or with few surface states, then the first term of equation (2) becomes the barrier height relevant share of z. B. determined at least 10%, then the second conductive material is selected so that the second work function is approximately equal to the sum of the electron affinity and the bandgap or equal to the sum. Like the first work function, the second work function may depend on the ratio of main constituents of the second conductive material to each other, so that the actual work function in the context of manufacturing tolerances of a predetermined value, for. B. the sum of electron affinity and band gap may differ.
Gemäß einer weiteren Ausführungsform bestimmt der zweite Term der Gleichung (2) zu einem maßgeblichen Anteil von z. B. mindestens 10% die Barrierenhöhe. Dann kann das zweite leitfähige Material so gewählt werden, dass die zweite Austrittsarbeit größer der Summe aus der Elektronenaffinität und dem Bandabstand ist, so dass über den ersten Term der Gleichung (2) der zweite Term teilweise oder vollständig kompensiert werden kann.According to one In another embodiment, the second term determines the equation (2) to a significant proportion of z. At least 10% the barrier height. Then the second conductive Material should be chosen so that the second work function greater the sum of the electron affinity and the band gap is such that over the first term of the equation (2) the second term is partially or fully compensated can be.
Gemäß anderen Ausführungsformen weicht die Austrittsarbeit eines der beiden Materialien um nicht mehr als den halben Bandabstand des Halbleitermaterials von der Elektronenaffinität des Halbleitermaterials und die Austrittsarbeit des zweiten Materials um nicht mehr als um den halben Bandabstand von der Summe aus der Elektronenaffinität und dem Bandabstand ab. Im Gleichgewichtsfall definieren Elektronenaffinität und Bandabstand die Lage von Leitungsband- und Valenzbandniveau. Vereinfachend könnte daher auch auf eine Anpassung der Austrittsarbeiten an das Leitungsband- bzw. Valenzbandniveau Bezug genommen werden.According to others Embodiments gives way to the work function of one of two materials by no more than half the band gap of the Semiconductor material of the electron affinity of the semiconductor material and the work function of the second material by no more than by half the band gap from the sum of the electron affinity and the band gap. In the equilibrium case define electron affinity and bandgap the location of conduction band and valence band level. Simplifying could therefore also be an adaptation of the work functions be referred to the conduction band or valence band level.
Der
erste Teilbereich
Die
erste und die zweite Kontaktstruktur
Die
Kontakte
Beispielsweise weicht die Austrittsarbeit des ersten leitfähigen Materials um nicht mehr als 0,2 eV, z. B. um nicht mehr als 0,1 eV von der Elektronenaffinität im Halbleitermaterial ab („Leitungsband-Anpassung”), während die Austrittsarbeit des zweiten leitfähigen Materials um nicht mehr als 0,2 eV, z. B. um nicht mehr als 0,1 eV von der Summe aus Elektronenaffinität und Bandabstand abweicht („Valenzband-Anpassung”). In solchen Fällen ist die absolute Barrierenhöhe niedrig genug, um von thermisch angeregten Ladungsträgern in ausreichender Zahl überwunden zu werden, so dass sich auch für „weite” Barrieren, die für ein direktes Tunneln zu dick sind, ein ausreichender Ladungsträgertransport ergibt.For example gives way to the work function of the first conductive material by not more than 0.2 eV, e.g. B. by not more than 0.1 eV of the Electron affinity in the semiconductor material ("conduction band adaptation"), while the work function of the second conductive Materials by not more than 0.2 eV, z. B. by not more than 0.1 eV of the sum of electron affinity and band gap deviates ("valence band adjustment"). In such Cases, the absolute barrier height is low enough to get enough of thermally excited charge carriers Number, so that even for "wide" barriers, which are too thick for direct tunneling, sufficient Carrier transport results.
Nach einer Ausführungsform können beide Materialien Silizide sein, beispielsweise das erste Material PtTiSi, PtSi, Pt2Si, IrSi, PdSi, Pd2Si, RhSi, YSi, or Zr2Si und das zweite Material VSi, ErSi, ZrSi2, HfSi, MoSi2, NiSi, CrSi2 oder TiSi oder umgekehrt. Nach einer anderen Ausführungsform ist eines der beiden leitfähigen Materialien ein Silizid und das andere kein Silizid. Gemäß weiteren Ausführungsformen ist keines der Materialien ein Silizid. Beispielsweise ist mindestens eines der beiden Materialien ein Metall, ein Metalloxid, oder ein Metallnitrid oder sind beide Materialien Metalle, Metalloxide oder Materialnitride. Zum Beispiel sind beide Materialien Metallnitride mit unterschiedlichem Stickstoff-Gehalt und/oder Korngröße. Zum Beispiel ist eines der Materialien ein Wolframnitrid mit einem Verhältnis von Wolfram zu Stickstoff von 1:1 oder kleiner, z. B. 0,9, und das andere Material ist ein Wolframnitrid mit einem Verhältnis von Wolfram zu Stickstoff von 1,2:1 oder größer, zum Beispiel 1,5.According to one embodiment, both materials may be silicides, for example the first material PtTiSi, PtSi, Pt 2 Si, IrSi, PdSi, Pd 2 Si, RhSi, YSi or Zr 2 Si and the second material VSi, ErSi, ZrSi 2 , HfSi, MoSi 2 , NiSi, CrSi 2 or TiSi or vice versa. In another embodiment, one of the two conductive materials is a silicide and the other is not a silicide. According to further embodiments, none of the materials is a silicide. For example, at least one of the two materials is a metal, a metal oxide, or a metal nitride, or both materials are metals, metal oxides or nitrides of materials. For example, both materials are metal nitrides with different nitrogen content and / or grain size. For example, one of the materials is a tungsten nitride having a ratio of tungsten to nitrogen of 1: 1 or less, e.g. 0.9, and the other material is a tungsten nitride having a ratio of tungsten to nitrogen of 1.2: 1 or greater, for example 1.5.
Die
Kontaktstrukturen
Die
Die
Kontaktstruktur
Gemäß einer Ausführungsform weicht die Austrittsarbeit des einen Materials um nicht mehr als 0,1 eV von der Elektronenaffinität und die Austrittsarbeit des anderen Materials um nicht mehr als 0,1 eV von der Summe aus Elektronenaffinität und Bandabstand ab. Gemäß anderen Ausführungsformen entspricht der Unterschied zwischen den Austrittsarbeiten des ersten und des zweiten Materials mindestens dem halben Bandabstand des undotierten Halbleitermaterials.According to one Embodiment gives way to the work function of the one material by not more than 0.1 eV from the electron affinity and the work function of the other material by no more than 0.1 eV of the sum of electron affinity and band gap from. According to other embodiments corresponds the difference between the work functions of the first and the second material at least half the band gap of the undoped Semiconductor material.
Zwischen
den vertikalen oder näherungsweise vertikalen Abschnitten
der ersten und der zweiten Interface-Struktur
Ist
das Halbleitermaterial der Halbleiterstruktur
Nach einer weiteren Ausführungsform weisen beide Materialien dieselben Hauptbestandteile auf, z. B. ein Metall und Stickstoff, z. B. Wolframnitrid, und unterscheiden sich lediglich in ihrem Stickstoffgehalt und/oder ihrer Phase und/oder ihrer Korngröße. Zum Beispiel ist eines der Materialien stickstoffreiches Wolframnitrid, in dem der Wolframgehalt kleiner ist als der Stickstoffgehalt, z. B. W0.9N mit einer Austrittsarbeit von 5,1 eV und das zweite Material wolframreiches Wolframnitrid, mit einem Wolframanteil, der deutlich höher ist als der Stickstoffanteil, z. B. W1.5N mit einer Austrittsarbeit von etwa 4,3 eV.According to another embodiment, both materials have the same main components, for. As a metal and nitrogen, z. As tungsten nitride, and differ only in their nitrogen content and / or their phase and / or their grain size. For example, one of the materials is nitrogen-rich tungsten nitride in which the tungsten content is less than the nitrogen content, e.g. B. W 0.9 N with a work function of 5.1 eV and the second material tungsten-rich tungsten nitride, with a tungsten content that is significantly higher than the nitrogen content, z. B. W 1.5 N with a work function of about 4.3 eV.
Die
Die
in der
Beide
Interface-Strukturen
Das
erste und das zweite Material sind bezüglich ihrer Austrittsarbeiten
an das Valenzband bzw. an das Leitungsband des Halbleitermaterials angepasst,
so dass die Barrierenhöhen reduziert sind. Ein zentraler
Abschnitt der Kontaktstruktur
Die
Die
Gemäß anderen
Ausführungsformen entfällt die Isolatorstruktur
Entsprechend
der
Die
Grabenisolationen
Die
Gemäß der
Gemäß einer
Ausführungsform besteht die Kontaktstruktur
Die
Gemäß der
Beispielsweise
mittels eines photolithografischen Verfahrens wird eine Kontaktöffnung
Mittels
eines geeigneten Abscheidungsverfahrens, z. B. ALD (atomic layer
deposition), CVD (chemical vapor deposition), PE-CVD (plasma enhanced
chemical vapor deposition), PVD (physical vapor deposition) oder
Molekularstrahl-Epitaxie wird eine 5 bis 15 nm, z. B. etwa 10 nm
dicke erste Schicht
Mittels
eines weiteren Abscheidungsverfahrens, z. B. eines der oben genannten,
kann eine dünne erste Maskenschicht
Entsprechend
der
Wie
in der
Die
Ein
erstes Füllmaterial wird z. B. in der Art eines konformalen
Liners aufgetragen. Das erste Füllmaterial ist beispielsweise
ein Material, dessen Leitfähigkeit größer
ist als die des ersten Materials der ersten Vorläuferschicht,
z. B. Wolfram, Aluminium, Silber oder Kupfer. Mittels einer gerichteten,
anisotropen Ätzung werden horizontale Abschnitte des ersten
Füllmaterials entfernt, wobei remanente Abschnitte des
ersten Füllmaterials eine sich entlang der Innenwand der
Kontaktöffnung
Wie
in der
Eine
z. B. konformale zweite Vorläuferschicht kann abgeschieden
werden, die die verbleibende Kontaktöffnung
Die
Die
Das
elektronische System
Die
Prozessoreinrichtung
Das
elektronische System
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- - EP 0590652 A2 [0002] - EP 0590652 A2 [0002]
- - US 5930616 [0003] US 5930616 [0003]
- - US 2006/0163670 [0004] US 2006/0163670 [0004]
- - US 7354819 B2 [0004] US 7354819 B2 [0004]
- - US 2006/0220141 [0004] US 2006/0220141 [0004]
- - US 2006/0275968 A1 [0005] US 2006/0275968 A1 [0005]
Zitierte Nicht-PatentliteraturCited non-patent literature
- - Hideki Hasegawa: „Fermi Level Pinning and Schottky Barrier Height Control at Metal-Semiconductor Interfaces of InP and Related Materials”; Jpn J. App. Phys. Vol. 38 (1999) pp. 1098–1102 [0005] Hideki Hasegawa: "Fermi Level Pinning and Schottky Barrier Height Control at Metal-Semiconductor Interfaces of InP and Related Materials"; Jpn J. App. Phys. Vol. 38 (1999) pp. 1098-1102 [0005]
Claims (36)
Priority Applications (1)
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DE102010004230A DE102010004230A1 (en) | 2009-01-23 | 2010-01-09 | Integrated circuit for use in e.g. electronic system, has interface-structures directly connected to doped area in respective partial areas of contact surface, where structures are made from respective conducting materials |
Applications Claiming Priority (3)
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DE102009005984.9 | 2009-01-23 | ||
DE102009005984 | 2009-01-23 | ||
DE102010004230A DE102010004230A1 (en) | 2009-01-23 | 2010-01-09 | Integrated circuit for use in e.g. electronic system, has interface-structures directly connected to doped area in respective partial areas of contact surface, where structures are made from respective conducting materials |
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DE102010004230A1 true DE102010004230A1 (en) | 2010-10-14 |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0590652A2 (en) | 1992-09-29 | 1994-04-06 | Nec Corporation | Method of forming contact between diffused layer and wiring conductor semiconductor device |
US5930616A (en) | 1995-10-20 | 1999-07-27 | Micron Technology, Inc. | Methods of forming a field effect transistor and method of forming CMOS circuitry |
US20060163670A1 (en) | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Dual silicide process to improve device performance |
US20060220141A1 (en) | 2000-08-25 | 2006-10-05 | Besser Paul R | Low contact resistance cmos circuits and methods for their fabrication |
US20060275968A1 (en) | 2003-07-25 | 2006-12-07 | Siegfried Mantl | Method for producing a contact and electronic component comprising said type of contact |
US7354819B2 (en) | 2002-11-07 | 2008-04-08 | Kabushiki Kaisha Toshiba | Method of manufacturing CMOS with silicide contacts |
-
2010
- 2010-01-09 DE DE102010004230A patent/DE102010004230A1/en not_active Ceased
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0590652A2 (en) | 1992-09-29 | 1994-04-06 | Nec Corporation | Method of forming contact between diffused layer and wiring conductor semiconductor device |
US5930616A (en) | 1995-10-20 | 1999-07-27 | Micron Technology, Inc. | Methods of forming a field effect transistor and method of forming CMOS circuitry |
US20060220141A1 (en) | 2000-08-25 | 2006-10-05 | Besser Paul R | Low contact resistance cmos circuits and methods for their fabrication |
US7354819B2 (en) | 2002-11-07 | 2008-04-08 | Kabushiki Kaisha Toshiba | Method of manufacturing CMOS with silicide contacts |
US20060275968A1 (en) | 2003-07-25 | 2006-12-07 | Siegfried Mantl | Method for producing a contact and electronic component comprising said type of contact |
US20060163670A1 (en) | 2005-01-27 | 2006-07-27 | International Business Machines Corporation | Dual silicide process to improve device performance |
Non-Patent Citations (1)
Title |
---|
Hideki Hasegawa: "Fermi Level Pinning and Schottky Barrier Height Control at Metal-Semiconductor Interfaces of InP and Related Materials"; Jpn J. App. Phys. Vol. 38 (1999) pp. 1098-1102 |
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