DE102007047247A1 - Semiconductor component for use in semiconductor chip package, has electrode contact point arranged on substrate, where external connection having conductive liquid is arranged on point, and container arranged on point is filled with liquid - Google Patents
Semiconductor component for use in semiconductor chip package, has electrode contact point arranged on substrate, where external connection having conductive liquid is arranged on point, and container arranged on point is filled with liquid Download PDFInfo
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- DE102007047247A1 DE102007047247A1 DE102007047247A DE102007047247A DE102007047247A1 DE 102007047247 A1 DE102007047247 A1 DE 102007047247A1 DE 102007047247 A DE102007047247 A DE 102007047247A DE 102007047247 A DE102007047247 A DE 102007047247A DE 102007047247 A1 DE102007047247 A1 DE 102007047247A1
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Abstract
Description
Die Erfindung bezieht sich auf ein Halbleiterbauelement mit einem externen Anschluss auf einer Elektrodenkontaktstelle, die auf einem Halbleitersubstrat angeordnet ist, sowie auf ein Verfahren zur Herstellung desselben.The The invention relates to a semiconductor device having an external Connection on an electrode pad, on a semiconductor substrate is arranged, as well as a method for producing the same.
Da die Mikroelektronikindustrie fortfährt, zunehmend komplexe Bauelemente mit extrem kleinen Merkmalabmessungen zu entwickeln, wird das Erzeugen von zuverlässigen Zwischenverbindungssystemen zu einer signifikanten Herausforderung. Ein allgemeines Verfahren zum Anbringen einer Chippackung an einer Kompositleiterplatte (PCB) erfolgt mit einer Ball-Grid-Array(BGA)-Konfiguration. In dieser Konfiguration stellen Lotkugeln sowohl die elektrische als auch die mechanische Verbindung zwischen der Chippackung und der PCB bereit.There the microelectronics industry continues to progressively complex components developing with extremely small feature dimensions will produce from reliable Interconnect systems to a significant challenge. A general method for attaching a chip package to a Composite printed circuit board (PCB) uses a Ball Grid Array (BGA) configuration. In this configuration, solder balls make both the electrical as well as the mechanical connection between the chip package and ready for the PCB.
Der Prozess zum Koppeln der Chippackung an die PCB beinhaltet typischerweise einen oder mehrere Temperaturzyklen, wie einen Lotmittelaufschmelzschritt als ein Beispiel. Außerdem kann eine Zuverlässigkeitsprüfung die Betriebsumgebung des resultierenden Bauelements mittels Durchführen von extremen Temperaturzyklen simulieren. Wäh rend dieser Temperaturzyklen verursacht eine Fehlanpassung zwischen dem thermischen Ausdehnungskoeffizienten (CTE) des Chippackungssubstrats und dem CTE der PCB eine Lokalisierung mechanischer Spannung an den Lotkugeln. Die erzeugte mechanische Spannung ist proportional sowohl zur CTE-Fehlanpassung zwischen dem Chippackungssubstrat und der PCB als auch zur Temperaturänderung. Somit führen große Differenzen im CTE und große Temperaturvariationen zu einer hohen mechanischen Spannung, die an den Lotkugeln lokalisiert ist. Diese lokalisierte mechanische Spannung kann zu Rissen in den Lotkugeln führen. Selbst kleine Risse können zu einer Zunahme des Widerstands der Lotkugelverbindung führen, welche die Betriebszuverlässigkeit des resultierenden Bauelements nachteilig beeinflussen kann. Speziell ist die effektive Fläche für eine elektrische Leitung reduziert, wenn Risse in der Lotkugel auftreten, wodurch der Widerstand der Verbindung zunimmt. Wenn sich jedoch die Risse durch die Lotkugel hindurch fortsetzen können, zum Beispiel durch wiederholte Temperaturzyklen, kann die Lotkugelverbindung vollständig ausfallen, was eine Unterbrechung zwischen der Chippackung und der PCB verursacht.Of the The process of coupling the chip package to the PCB typically involves one or more temperature cycles, such as a solder reflow step for example. Furthermore can a reliability check the Operating environment of the resulting device by performing extreme Simulate temperature cycles. During this Temperature cycles causes a mismatch between the thermal Expansion coefficients (CTE) of the chip packaging substrate and the CTE the PCB a localization of mechanical stress on the solder balls. The generated stress is proportional to both the CTE mismatch between the chip package substrate and the PCB as well as the temperature change. Thus lead size Differences in CTE and big ones Temperature variations to a high mechanical stress, the localized on the solder balls. This localized mechanical Stress can lead to cracks in the solder balls. Even small cracks can too an increase in the resistance of the Lotkugelverbindung lead, which the operational reliability of the resulting device can adversely affect. specially is the effective area for one electrical conduction reduces when cracks occur in the solder ball, whereby the resistance of the connection increases. If, however, the cracks can continue through the solder ball, for example through repeated temperature cycles, the solder ball joint can Completely fail, what a break between the chip package and the PCB causes.
Ein
Verfahren zur Minimierung einer Ausbreitung von Rissen in Lotkugeln
ist in der Patentschrift
Der Erfindung liegt als technisches Problem die Bereitstellung eines Halbleiterbauelements der eingangs genannten Art sowie eines Verfahrens zur Herstellung desselben zugrunde, welche die oben erwähnten Schwierigkeiten des Standes der Technik reduzieren oder vermeiden und insbesondere eine Minimierung einer Rissausbreitung und/oder nachteiliger Effekte auf den Widerstand der externen Anschlussverbindung aufgrund von Rissen ermöglicht.Of the Invention is the technical problem of providing a Semiconductor component of the aforementioned type and a method for the preparation of the same, which the above-mentioned difficulties reduce or avoid the prior art and in particular a minimization of crack propagation and / or adverse effects on the resistance of the external connection connection due to Cracks possible.
Die Erfindung löst dieses Problem durch die Bereitstellung eines Halbleiterbauelements mit den Merkmalen des Anspruchs 1, 18 oder 19 und eines Verfahrens mit den Merkmalen des Anspruchs 21. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben.The Invention solves this problem by providing a semiconductor device with the features of claim 1, 18 or 19 and a method with the features of claim 21. Advantageous developments The invention are specified in the subclaims.
Einige Ausführungsformen der Erfindung stellen ein Halbleiterbauelement mit einem Substrat, einer Elektrodenkontaktstelle, die auf dem Substrat angeordnet ist, einem externen Anschluss, der auf der Elektrodenkontaktstelle angeordnet ist, einem Behälter, der sich von der Elektrodenkontaktstelle in den externen Anschluss hinein erstreckt, und einer leitfähigen Flüssigkeit, die im Inneren des Behälters angeordnet ist, bereit. Die leitfähige Flüssigkeit wird fest, wenn sie Luft ausgesetzt wird. Wenn sich ein Riss in dem externen Anschluss bildet, unterdrückt der Behälter eine Ausbreitung des Risses. Wenn der Riss den Behälter durchbricht, füllt die leitfähige Flüssigkeit des Weiteren den Riss und kann sich in dem Riss verfestigen, wenn sie Luft ausgesetzt wird.Some embodiments of the invention provide a semiconductor device with a substrate, a Electrode pad, which is arranged on the substrate, a external terminal, which is arranged on the electrode pad is, a container, extending from the electrode pad into the external connector extends into it, and a conductive liquid inside the Container arranged is ready. The conductive liquid becomes solid when exposed to air. When a crack in the external connection, the container suppresses a spread of the tear. If the tear the container breaks through, fills the conductive one liquid Furthermore, the crack and can solidify in the crack, if she is exposed to air.
Gemäß der Erfindung wird eine Rissausbreitung innerhalb des externen Anschlusses unterdrückt. Wenn zum Beispiel ein Riss den Behälter durchbricht, der die leitfähige Flüssigkeit beinhaltet, füllt die leitfähige Flüssigkeit von dem Behälter den Riss, wobei der Widerstand, d.h. die Leitfähigkeitscharakteristika der Verbindung, wiederhergestellt wird. Daher weisen Verbindungen zwischen Chippackungen und PCBs gemäß Ausführungsformen der Erfindung eine verbesserte Zuverlässigkeit gegenüber den vorstehend erläuterten herkömmlichen Ausführungsformen auf.According to the invention, crack propagation within the external terminal is suppressed. For example, if a crack breaks through the container containing the conductive fluid, fills the conductive liquid from the container, the crack, whereby the resistance, ie the conductivity characteristics of the compound is restored. Therefore, connections between chip packages and PCBs according to embodiments of the invention have improved reliability over the conventional embodiments discussed above.
Vorteilhafte Ausführungsformen der Erfindung werden im Folgenden beschrieben und sind in den Zeichnungen gezeigt, die außerdem die vorstehend zum leichteren Verständnis der Erfindung erläuterte herkömmliche Ausführungsform zeigen. In den Zeichnungen sind:advantageous embodiments The invention will be described below and in the drawings shown that as well the conventional one explained above for easier understanding of the invention embodiment demonstrate. In the drawings are:
Die
Erfindung wird im Folgenden unter Bezugnahme auf die begleitenden
Die
Halbleiterchippackung
Der
Behälter
Ein
Teil
Wie vorstehend im Detail angegeben, stellen Ausführungsformen der Erfindung einen externen Anschluss mit einem mit einer leitfähigen Flüssigkeit gefüllten Behälter bereit. Eine Rissausbreitung innerhalb des externen Anschlusses wird durch den Behälter unterdrückt. Wenn der Riss des Weiteren den Behälter durchbricht, füllt die leitfähige Flüssigkeit von dem Behälter wenigstens teilweise den Riss, was die Widerstandscharakteristika der Verbindung verbessert oder wiederherstellt. Daher weisen Verbindungen zwischen Chippackungen und PCBs gemäß Ausführungsformen der Erfindung eine gegenüber herkömmlichen Verfahren verbesserte Zuverlässigkeit auf.As set forth in detail above, embodiments of the invention an external connection with a filled with a conductive liquid container ready. Crack propagation within the external connection is through the container suppressed. If the crack also breaks through the container, it fills conductive Liquid from the container at least partially the crack, what the resistance characteristics improves or restores the connection. Therefore, have connections between chip packages and PCBs according to embodiments of the invention one over conventional Method improved reliability on.
Verschiedene Vorgänge werden als mehrere diskrete Schritte beschrieben, die in einer Weise durchgeführt werden, die beim Verständnis der Erfindung am hilfreichsten ist. Die Reihenfolge, in der die Schritte beschrieben sind, impliziert jedoch nicht, dass die Vorgänge reihenfolge abhängig sind oder dass die Reihenfolge, in der die Schritte durchgeführt werden, die Reihenfolge sein muss, in der die Schritte präsentiert werden. Des Weiteren sind allgemein bekannte Strukturen und Bauelemente nicht gezeigt, um die Beschreibung der Erfindung nicht mit unnötigen Details zu verschleiern.Various operations are described as multiple discrete steps that are performed in a manner the understanding the invention is most helpful. The order in which the steps but does not imply that the operations are order-dependent or that the order in which the steps are performed the order in which the steps are presented must be become. Furthermore, well-known structures and components not shown to the description of the invention with unnecessary details to disguise.
Wenngleich die Erfindung in Verbindung mit dem langgestreckten Behälter erörtert wurde, ist der Behälter möglicherweise nicht langgestreckt oder kann in einer Weise langgestreckt sind, die sich von jener in den Zeichnungen gezeigten unterscheidet, solange der Behälter die gleiche Funktion des beschriebenen langgestreckten Behälters durchführt. Daher versteht es sich, dass das Vorstehende illustrativ für die Erfindung ist und nicht dazu gedacht ist, auf die spezifischen offenbarten Ausführungsformen beschränkt zu sein, und dass Modifikationen der offenbarten Ausführungsformen ebenso wie weiterer Ausführungsformen als in dem Umfang der beigefügten Ansprüche enthalten gedacht sind.Although the invention has been discussed in connection with the elongated container, is the container possibly not elongated or can be elongated in a way which differs from that shown in the drawings, as long as the container performs the same function of the described elongated container. Therefore It should be understood that the foregoing is illustrative of the invention is and is not meant to be revealed on the specific Embodiments to be limited and that modifications of the disclosed embodiments as well as other embodiments as to the extent of the attached claims are thought to contain.
Claims (36)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
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KR10-2006-0097307 | 2006-10-02 | ||
KR20060097307 | 2006-10-02 | ||
KR1020060121657A KR101328551B1 (en) | 2006-10-02 | 2006-12-04 | Semiconductor devices |
KR10-2006-0121657 | 2006-12-04 | ||
US11/858,078 | 2007-09-19 | ||
US11/858,078 US7675171B2 (en) | 2006-10-02 | 2007-09-19 | Semiconductor package and fabricating method thereof |
Publications (1)
Publication Number | Publication Date |
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DE102007047247A1 true DE102007047247A1 (en) | 2008-05-15 |
Family
ID=39277837
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Application Number | Title | Priority Date | Filing Date |
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DE102007047247A Withdrawn DE102007047247A1 (en) | 2006-10-02 | 2007-09-26 | Semiconductor component for use in semiconductor chip package, has electrode contact point arranged on substrate, where external connection having conductive liquid is arranged on point, and container arranged on point is filled with liquid |
Country Status (2)
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JP (1) | JP2008091926A (en) |
DE (1) | DE102007047247A1 (en) |
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JP5642623B2 (en) | 2011-05-17 | 2014-12-17 | 株式会社東芝 | Semiconductor light emitting device |
-
2007
- 2007-09-26 DE DE102007047247A patent/DE102007047247A1/en not_active Withdrawn
- 2007-10-02 JP JP2007259037A patent/JP2008091926A/en active Pending
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JP2008091926A (en) | 2008-04-17 |
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