DE102006060634A1 - Method for producing an electrical resistance on a substrate - Google Patents
Method for producing an electrical resistance on a substrate Download PDFInfo
- Publication number
- DE102006060634A1 DE102006060634A1 DE102006060634A DE102006060634A DE102006060634A1 DE 102006060634 A1 DE102006060634 A1 DE 102006060634A1 DE 102006060634 A DE102006060634 A DE 102006060634A DE 102006060634 A DE102006060634 A DE 102006060634A DE 102006060634 A1 DE102006060634 A1 DE 102006060634A1
- Authority
- DE
- Germany
- Prior art keywords
- substrate
- layer
- silver
- palladium
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
- H01C17/06506—Precursor compositions therefor, e.g. pastes, inks, glass frits
- H01C17/06513—Precursor compositions therefor, e.g. pastes, inks, glass frits characterised by the resistive component
- H01C17/06526—Precursor compositions therefor, e.g. pastes, inks, glass frits characterised by the resistive component composed of metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/003—Thick film resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49082—Resistor making
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49082—Resistor making
- Y10T29/49099—Coating resistive material on a base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12771—Transition metal-base component
- Y10T428/12861—Group VIII or IB metal-base component
- Y10T428/12944—Ni-base component
Abstract
Description
Die Erfindung betrifft ein Verfahren zur Herstellung eines elektrischen Widerstands, insbesondere Stromfühlerwiderstands, auf einem Substrat, wobei ein Widerstandsrohling auf das Substrat aufgebracht und anschließend zur Bildung des Widerstands temperaturbehandelt wird.The The invention relates to a method for producing an electrical Resistance, in particular current sensor resistance, on a substrate, with a resistor blank on the substrate applied and then is temperature treated to form the resistor.
Stand der TechnikState of the art
Es ist bekannt, elektrische Widerstände, insbesondere Stromfühlerwiderstände, auf Substraten herzustellen. Dies erfolgt insbesondere in Dickschichttechnik und LTCC-Technik (LTCC = low temperature cofire ceramic). Hierzu werden Silberpalladium-Pasten im Siebdruckverfahren auf das Substrat aufgedruckt. Die Integration solcher insbesondere als Leiterbahnwiderstände ausgebildeten Widerstände mit typischen Widerstandswerten von zum Beispiel 100 mOhm und Temperaturkoeffizient-Werten von zum Beispiel 100 ppm/K erfordern hohe Prozessaufwendungen, wie zum Beispiel das Anschließen dieses Widerstandes mit hochsilberhaltigen, niederohmigen Leiterbahnen, gleichzeitig ist das Anbringen von Zwischenlegierungen (intermediates) erforderlich, was zusätzliche Aufdruckschritte und Temperaturbehandlungsschritte erfordert. Derartige Zusatzschritte sind oftmals aufgrund der Auslegung der Fertigungslinien gar nicht möglich. Die aufgedruckten Silberpalladiumpasten, die einen vorgemischten Widerstand darstellen, werden zur Fertigstellung des Widerstandes gebrannt, also temperaturbehandelt.It is known, electrical resistances, in particular current sensor resistors, on Produce substrates. This is done especially in thick film technology and LTCC technology (LTCC = low temperature cofire ceramic). For this Silver palladium pastes are screen printed on the substrate. The integration of such in particular designed as conductor resistances resistors with typical resistance values of for example 100 mOhm and temperature coefficient values of For example, 100 ppm / K requires high process costs, such as Example connecting this Resistance with high silver, low-resistance tracks, at the same time the application of intermediate alloys (intermediates) required, what additional Imprinting steps and temperature treatment steps required. such Additional steps are often due to the design of the production lines not possible at all. The printed silver palladium pastes which are a premixed Resist, become the completion of the resistance fired, so temperature treated.
Offenbarung der ErfindungDisclosure of the invention
Aufgrund des erfindungsgemäßen Verfahrens zur Herstellung eines elektrischen Widerstands, insbesondere Stromfühlerwiderstands, auf einem Substrat wird ein Widerstandsrohling auf das Substrat aufgebracht und anschließend zur Bildung des Widerstands temperaturbehandelt, wobei zur Bildung des Widerstandsrohlings eine Palladiumschicht auf das Substrat aufgebracht und anschließend auf die Palladiumschicht eine Silberschicht aufgebracht wird. Alternativ wird eine Silberschicht auf das Substrat und auf die Silberschicht eine Palladiumschicht aufgebracht. Danach erfolgt eine Temperaturbehandlung, sodass das Palladium der Palladiumschicht mit dem Silber der Silberschicht durchlegiert. Diese Legierung stellt dann den gewünschten Widerstand, insbesondere Stromfühlerwiderstand, dar. Die Herstellung dieses Widerstands erfolgt in einem so genannten cofire-Prozess, das heißt, in situ, also am Ort und während des Brennschrittes wird aus dem Widerstandsrohling der elektrische Widerstand gebildet. Damit besteht gegenüber dem bisherigen Verfahren ein entscheidender Unterschied, da sich aufgrund der Temperaturbehandlung eine den Widerstand bildende Legierung bildet, und zwar aufgrund der Durchlegierung getrennter Schichten, während im Stand der Technik vor dem Brennprozess fertiggestellte Silberpalladiumpaste verwendet wird, die nach dem insbesondere per Siebdruck erfolgenden Aufbringen gebrannt wird. Die Einstellung der Parameter des Widerstandes erfolgt durch eine entsprechend gewählte Menge an Palladium relativ zur Silbermenge. Auf diese Art und Weise lässt sich sowohl der Widerstandswert als auch der Temperaturkoeffizient (TK-Wert) in gewünschter Weise einstellen. Bei dem Temperaturkoeffizienten handelt es sich um eine Angabe, um wie viel Ohm sich jedes Ohm des Widerstandes pro °K ändert. Aufgrund des erfindungsgemäßen Vorgehens treten keine Diffusionszonen, insbesondere beim Kontaktieren von angrenzenden Anschlusszonen, auf und es ist ferner sichergestellt, dass sich keine Kirkendall-Hohlräume (Kirkendall-Voids) bilden. Derartige Diffusionszonen mit Voidbildungen führen zu Zuverlässigkeitsproblemen aufgrund von Driften oder gar Leiterbahnabrissen. Von besonderer Bedeutung ist, dass das Palladium separat aufgebracht und – zusammen mit dem Silber – der Widerstandswert durch Legierungsbildung im cofire-Prozess eingestellt wird. Im Gegensatz dazu wird üblicherweise eine fertig gemischte Silberpalladiumpaste verwendet, die mit Zusatzschritten, wie Drucken und Brennen, aufgebracht wird und über zusätzlich aufgebrachte Zwischenlegierungen an den Anschlusszonen kontaktiert werden.by virtue of the method according to the invention for producing an electrical resistance, in particular current sensor resistance, on a substrate becomes a resistance blank on the substrate applied and then thermally treated to form the resistor, wherein the formation of the resistor blank a palladium layer applied to the substrate and then on the palladium layer is applied a silver layer. alternative is a silver layer on the substrate and on the silver layer applied a palladium layer. Thereafter, a temperature treatment, so that the palladium of the palladium layer with the silver of the silver layer shorted. This alloy then provides the desired Resistance, in particular current sensor resistance, dar. The production of this resistor takes place in a so-called cofire process, that is, in situ, ie at the place and during of the firing step is from the resistance blank of the electric Resistance formed. This is compared to the previous procedure a crucial difference, since due to the temperature treatment forms a resistor forming alloy, due to the Alloying of separate layers while in the prior art used before the firing process completed silver palladium paste is, after applying in particular by screen printing applying is burned. The adjustment of the parameters of the resistance takes place by an appropriately chosen Amount of palladium relative to the amount of silver. In this way let yourself both the resistance value and the temperature coefficient (TK value) in the desired Set way. The temperature coefficient is To give an indication of how much ohm each ohm of resistance changes per ° K. by virtue of the procedure of the invention There are no diffusion zones, especially when contacting adjacent connecting zones, and it is further ensured that no Kirkendall cavities (Kirkendall voids) form. Such diffusion zones with void formations lead to it Reliability problems due drifts or even conductor breaks. Really important is that the palladium is applied separately and - together with the silver - the resistance value by alloy formation in the cofire process. In contrast this is usually used a ready-mixed silver palladium paste, which with additional steps, such as printing and firing, is applied and additionally applied intermediate alloys be contacted at the connection zones.
Nach einer Weiterbildung der Erfindung ist vorgesehen, dass das Aufbringen der Palladiumschicht und/oder der Silberschicht im Druckverfahren erfolgt. Insbesondere wird das Druckverfahren als Siebdruckverfahren durchgeführt.To a development of the invention is provided that the application the palladium layer and / or the silver layer is carried out in the printing process. In particular, the printing process is carried out as a screen printing process.
Mithin wird im Siebdruckverfahren zunächst die Palladiumschicht und darauf die Silberschicht aufgebracht.therefore is first screenprinted the Palladium layer and then applied the silver layer.
Ferner ist es vorteilhaft, wenn die Silberschicht die Palladiumschicht zur Ausbildung von elektrischen Anschlusszonen seitlich überragt. Mithin bildet sich die Legierung nur im Überlappungsbereich von Silber und Palladium und die überragenden Silberschichtabschnitte können zur Ausbildung von elektrischen Anschlusszonen genutzt werden, die vorzugsweise mit Silber-Durchkontaktierungen des Substrats verbunden werden.Further it is advantageous if the silver layer is the palladium layer projected laterally for the formation of electrical connection zones. Thus, the alloy forms only in the overlap region of silver and palladium and the towering ones Silver layer sections can be used to form electrical connection zones, preferably with silver vias of the substrate.
Ferner ist von Vorteil, wenn auf den Widerstandsrohling eine Abdeckglasschicht aufgebracht wird. Diese wird vorzugsweise aufgedruckt, insbesondere per Siebdruck, wobei die Abdeckglasschicht vor der Temperaturbehandlung aufgebracht wird. Es handelt sich dabei also zunächst um noch nicht gebranntes Glas, das durch die Temperaturbehandlung dann gebrannt wird. Die Abdeckglasschicht schützt den elektrischen Widerstand.Further is advantageous if a cover glass layer on the resistance blank is applied. This is preferably printed, in particular by screen printing, wherein the cover glass layer before the temperature treatment is applied. It is thus first of all not burnt Glass that is then fired by the temperature treatment. The Cover glass layer protects the electrical resistance.
Nach einer Weiterbildung der Erfindung ist vorgesehen, dass die Palladiumschicht unter zumindest bereichsweise erfolgender Zwischenschaltung eines Haftvermittlers auf das Substrat aufgebracht wird. In einem solchen Falle befindet sich also die Palladiumschicht auf dem Substrat, das heißt, nicht unmittelbar, sondern unter Zwischenschaltung des Haftvermittlers, sodass die Palladiumschicht sicher auf dem Substrat gehalten wird. Anschließend wird die Palladiumschicht dann mit der Silberschicht versehen.To a development of the invention, it is provided that the palladium layer under at least partially successful interposition of a Adhesive is applied to the substrate. In such a Trap is thus the palladium layer on the substrate, this means, not immediately, but with the interposition of the adhesion agent, so that the palladium layer is securely held on the substrate. Subsequently the palladium layer is then provided with the silver layer.
Es ist vorteilhaft, wenn die Schichten als Leiterbahnschichten ausgebildet werden. Demzufolge handelt es sich um Strukturen, die leiterbahnähnlich ausgebildet sind, das heißt ein Leiterbahnabschnitt bildet den erwähnten elektrischen Widerstand, insbesondere Stromfühlerwiderstand. Auch die Abdeckglasschicht kann leiterbahnähnlich ausgebildet sein, was nicht bedeutet, dass eine elektrische Leitfähigkeit bei der Abdeckglasschicht vorliegt, sondern dass die Abdeckglasschicht die Formgebung einer Leiterbahn besitzt.It is advantageous if the layers are formed as interconnect layers become. Accordingly, it is structures that are similar to a track are, that is a track section forms the mentioned electrical resistance, in particular current sensor resistance. The cover glass layer may be formed like a track, which does not mean that an electrical conductivity in the cover glass layer but that the Abdeckglasschicht the shape of a Conductor track owns.
Es ist ferner vorteilhaft, wenn der Haftvermittler ebenfalls durch einen Druckprozess, insbesondere durch einen Siebdruckprozess, aufgebracht wird.It is also advantageous if the bonding agent also by a printing process, in particular applied by a screen printing process becomes.
Ferner ist es vorteilhaft, wenn das Verfahren in Dickschichttechnik erfolgt.Further it is advantageous if the process takes place in thick film technology.
Als Substrat kann insbesondere ein Keramiksubstrat verwendet werden, wobei es sich insbesondere um LTCC-Keramik handeln kann, also um low temperature cofired ceramic. Das Keramiksubstrat kann mittels mehrerer, aufeinander geschichteter Keramikfolien ausgebildet werden. Zwischen den Keramikfolien befinden sich vorzugsweise Leiterbahnschichten, sodass eine mehrlagige Leiterbahnstruktur entsteht.When Substrate can be used in particular a ceramic substrate, which may in particular be LTCC ceramic, ie low temperature cofired ceramic. The ceramic substrate can by means of several, layered ceramic films are formed. Between the ceramic films are preferably conductor track layers, so that a multilayer interconnect structure is created.
Nach einer Weiterbildung der Erfindung ist vorgesehen, dass die elektrischen Anschlusszonen als Durchkontaktierungen, insbesondere Silberdurchkontaktierungen (Silber-Via) ausgebildet werden.To a development of the invention, it is provided that the electrical Terminal zones as plated-through holes, in particular silver plated holes (Silver via) are formed.
Schließlich betrifft die Erfindung ein Substrat mit einem elektrischen Widerstand, insbesondere Stromfühlerwiderstand, wobei die Herstellung gemäß dem vorstehend erwähnten Verfahren erfolgt.Finally, concerns the invention a substrate with an electrical resistance, in particular current sensor resistance, wherein the preparation according to the above mentioned Procedure is done.
Kurze Beschreibung der ZeichnungShort description of the drawing
Die Zeichnung veranschaulicht die Erfindung anhand eines Ausführungsbeispiels, und zwar zeigt die Figur einen Querschnitt durch ein mit elektrischen Widerstand, insbesondere Stromfühlerwiderstand, versehenes Substrat.The Drawing illustrates the invention with reference to an embodiment, namely, the figure shows a cross section through an electrical resistance, in particular current sensor resistance, provided Substrate.
Ausführungsform der ErfindungEmbodiment of the invention
Die
Figur zeigt ein Substrat
Das
Substrat
Um
zwischen den Silberkontaktierungen
Nach
den vorstehend erwähnten
Arbeitsschritten wird mittels eines Einbrennprozesses, also in einem
gemeinsamen Brennschritt, zusammen mit dem als Mehrlagenkeramik
ausgebildeten Substrat der Widerstand
Zusätzlich ist
es möglich,
dass vor dem Brennschritt über
die Silberschicht
Wie
sich aus dem Vorstehenden ergibt, wird durch das separate Anbringen
von Palladium und Silber eine Einstellung des Widerstandswerts entsprechend
der gewählten
Mengen vorbereitet und durch die anschließende Legierungsbildung im
cofire-Prozess der Widerstand
Claims (16)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102006060634A DE102006060634A1 (en) | 2006-12-21 | 2006-12-21 | Method for producing an electrical resistance on a substrate |
DE502007005443T DE502007005443D1 (en) | 2006-12-21 | 2007-11-02 | METHOD FOR PRODUCING AN ELECTRICAL RESISTANCE ON A SUBSTRATE |
US12/304,295 US8115589B2 (en) | 2006-12-21 | 2007-11-02 | Method for producing an electrical resistor on a substrate |
PCT/EP2007/061831 WO2008077671A1 (en) | 2006-12-21 | 2007-11-02 | Method for producing an electrical resistor on a substrate |
EP07847108A EP2127505B1 (en) | 2006-12-21 | 2007-11-02 | Method for producing an electrical resistor on a substrate |
AT07847108T ATE485705T1 (en) | 2006-12-21 | 2007-11-02 | METHOD FOR PRODUCING ELECTRICAL RESISTANCE ON A SUBSTRATE |
JP2009541936A JP4763833B2 (en) | 2006-12-21 | 2007-11-02 | Method for manufacturing electrical resistance on a substrate and substrate with current sensor resistance |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102006060634A DE102006060634A1 (en) | 2006-12-21 | 2006-12-21 | Method for producing an electrical resistance on a substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102006060634A1 true DE102006060634A1 (en) | 2008-06-26 |
Family
ID=39262787
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102006060634A Withdrawn DE102006060634A1 (en) | 2006-12-21 | 2006-12-21 | Method for producing an electrical resistance on a substrate |
DE502007005443T Active DE502007005443D1 (en) | 2006-12-21 | 2007-11-02 | METHOD FOR PRODUCING AN ELECTRICAL RESISTANCE ON A SUBSTRATE |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE502007005443T Active DE502007005443D1 (en) | 2006-12-21 | 2007-11-02 | METHOD FOR PRODUCING AN ELECTRICAL RESISTANCE ON A SUBSTRATE |
Country Status (6)
Country | Link |
---|---|
US (1) | US8115589B2 (en) |
EP (1) | EP2127505B1 (en) |
JP (1) | JP4763833B2 (en) |
AT (1) | ATE485705T1 (en) |
DE (2) | DE102006060634A1 (en) |
WO (1) | WO2008077671A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019008004A1 (en) * | 2017-07-04 | 2019-01-10 | Rogers Germany Gmbh | Method for producing a via in a carrier layer produced from a ceramic and carrier layer having a via |
Citations (7)
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DE1646874A1 (en) * | 1965-03-25 | 1971-09-09 | Du Pont | Conductive composition |
EP0415571A2 (en) * | 1989-08-07 | 1991-03-06 | Ford Motor Company Limited | Layered thick film resistors and method for producing same |
EP0417749A2 (en) * | 1989-09-13 | 1991-03-20 | Amp-Akzo Corporation | Thick film resistor/integrated circuit substrate and method of manufacture |
DE19953594A1 (en) * | 1998-11-20 | 2000-05-25 | Matsushita Electric Ind Co Ltd | Surface-mounted electronic component, e.g. a capacitor, has electrodes of migration resistant material formed on the entire surface of a substrate |
DE19780905C2 (en) * | 1996-08-27 | 2003-03-20 | Kamaya Electric Co | Resistance and process for its manufacture |
DE10144364A1 (en) * | 2001-09-10 | 2003-04-03 | Epcos Ag | Electrical multilayer component |
DE69829018T2 (en) * | 1997-06-10 | 2006-03-23 | Canon K.K. | Substrate and process for its preparation |
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JPS5852900A (en) * | 1981-09-24 | 1983-03-29 | 株式会社日立製作所 | Method of producing ceramic multilayer circuit board |
JPH0691323B2 (en) * | 1989-02-25 | 1994-11-14 | 大陽誘電株式会社 | Low temperature firing type ceramic multilayer wiring board |
DE3915106A1 (en) | 1989-05-09 | 1990-11-15 | Haendler Metall & Masch | DEVICE FOR EXHAUSTING A BODY, IN PARTICULAR A PACK OF GOODS |
US5221644A (en) * | 1991-12-13 | 1993-06-22 | Delco Electronics Corporation | Thick film sense resistor composition and method of using the same |
US5345212A (en) * | 1993-07-07 | 1994-09-06 | National Starch And Chemical Investment Holding Corporation | Power surge resistor with palladium and silver composition |
JPH07320534A (en) | 1994-05-26 | 1995-12-08 | Mitsubishi Materials Corp | Thick film conductor, its forming method and method of using this conductor |
JP3093601B2 (en) | 1994-09-28 | 2000-10-03 | 株式会社住友金属エレクトロデバイス | Ceramic circuit board |
JPH1117343A (en) * | 1997-06-24 | 1999-01-22 | Tdk Corp | Manufacture of ceramic substrate |
US5889445A (en) * | 1997-07-22 | 1999-03-30 | Avx Corporation | Multilayer ceramic RC device |
JPH11195505A (en) * | 1997-12-26 | 1999-07-21 | E I Du Pont De Nemours & Co | Thick-film resistor and manufacture thereof |
US7127809B2 (en) * | 2004-03-18 | 2006-10-31 | Northrop Grumman Corporation | Method of forming one or more base structures on an LTCC cofired module |
-
2006
- 2006-12-21 DE DE102006060634A patent/DE102006060634A1/en not_active Withdrawn
-
2007
- 2007-11-02 US US12/304,295 patent/US8115589B2/en not_active Expired - Fee Related
- 2007-11-02 WO PCT/EP2007/061831 patent/WO2008077671A1/en active Application Filing
- 2007-11-02 AT AT07847108T patent/ATE485705T1/en active
- 2007-11-02 JP JP2009541936A patent/JP4763833B2/en not_active Expired - Fee Related
- 2007-11-02 DE DE502007005443T patent/DE502007005443D1/en active Active
- 2007-11-02 EP EP07847108A patent/EP2127505B1/en not_active Not-in-force
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Cited By (1)
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---|---|---|---|---|
WO2019008004A1 (en) * | 2017-07-04 | 2019-01-10 | Rogers Germany Gmbh | Method for producing a via in a carrier layer produced from a ceramic and carrier layer having a via |
Also Published As
Publication number | Publication date |
---|---|
DE502007005443D1 (en) | 2010-12-02 |
EP2127505B1 (en) | 2010-10-20 |
JP2010514175A (en) | 2010-04-30 |
WO2008077671A1 (en) | 2008-07-03 |
US8115589B2 (en) | 2012-02-14 |
ATE485705T1 (en) | 2010-11-15 |
EP2127505A1 (en) | 2009-12-02 |
JP4763833B2 (en) | 2011-08-31 |
US20100039213A1 (en) | 2010-02-18 |
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