DE102004027787A1 - Semiconductor devices with plastic housing and method of making the same - Google Patents
Semiconductor devices with plastic housing and method of making the same Download PDFInfo
- Publication number
- DE102004027787A1 DE102004027787A1 DE102004027787A DE102004027787A DE102004027787A1 DE 102004027787 A1 DE102004027787 A1 DE 102004027787A1 DE 102004027787 A DE102004027787 A DE 102004027787A DE 102004027787 A DE102004027787 A DE 102004027787A DE 102004027787 A1 DE102004027787 A1 DE 102004027787A1
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- Prior art keywords
- system carrier
- semiconductor
- semiconductor chip
- carrier strip
- wiring structure
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 176
- 239000004033 plastic Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 8
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- 238000000034 method Methods 0.000 claims description 43
- 239000004416 thermosoftening plastic Substances 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000003475 lamination Methods 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- 230000005496 eutectics Effects 0.000 claims description 4
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- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 239000012815 thermoplastic material Substances 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
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- 238000010438 heat treatment Methods 0.000 description 5
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- 238000005516 engineering process Methods 0.000 description 4
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- 239000000969 carrier Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
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- 230000018109 developmental process Effects 0.000 description 2
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- 230000009471 action Effects 0.000 description 1
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- 239000012141 concentrate Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000004413 injection moulding compound Substances 0.000 description 1
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Classifications
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
Die Erfindung betrifft ein Halbleiterbauteil mit Kunststoffgehäuse und Halbleiterchip (2). Der Halbleiterchip (2) ist auf einer Montageseite (3) eines Systemträgers (4) montiert. Der Systemträger (4) weist eine Verdrahtungsstruktur (5) auf, die über elektrische Verbindungselemente (6) mit dem Halbleiterchip (2) mechanisch und elektrisch in Verbindung steht. Das Kunststoffgehäuse weist eine eingeebnete, thermoplastische Kunststoffmasse (7) auf, die den Halbleiterchip (2) und die Verbindungselemente (6) einbettet und auf der Montageseite (3) des Systemträgers (4) angeordnet ist.The invention relates to a semiconductor device with plastic housing and semiconductor chip (2). The semiconductor chip (2) is mounted on a mounting side (3) of a system carrier (4). The system carrier (4) has a wiring structure (5) which is mechanically and electrically connected to the semiconductor chip (2) via electrical connection elements (6). The plastic housing has a leveled, thermoplastic plastic compound (7), which embeds the semiconductor chip (2) and the connecting elements (6) and is arranged on the mounting side (3) of the system carrier (4).
Description
Die Erfindung betrifft ein Halbleiterbauteil mit Kunststoffgehäuse und Verfahren zur Herstellung desselben. Dabei weist das Halbleiterbauteil zumindest ein Halbleiterchip auf, der auf einer Montageseite eines Systemträgers montiert ist. Der Systemträger weist eine Verdrahtungsstruktur auf, mit welcher der Halbleiterchip elektrisch und mechanisch verbunden ist.The The invention relates to a semiconductor device with plastic housing and Process for producing the same. In this case, the semiconductor device at least one semiconductor chip on a mounting side of a leadframe is mounted. The system carrier has a wiring structure with which the semiconductor chip electrically and mechanically connected.
Die Komponenten eines Halbleiterbauteils, wie Halbleiterchip, elektrische Verbindungselemente, und/oder elektrische Verdrahtungsstrukturen werden durch eine Kunststoffmasse, in welche die Komponenten eingebettet sind, geschützt. Für ein Aufbringen der schützenden Kunststoffmasse werden bisher zwei aufwendige, kostenintensive Verfahren eingesetzt.The Components of a semiconductor device, such as semiconductor chip, electrical Connecting elements, and / or electrical wiring structures be through a plastic mass, in which the components embedded are protected. For a Apply the protective Plastic compound are so far two expensive, costly process used.
Bei einem ersten Verfahren werden die Komponenten mit einer Pressmasse umhüllt. Bei diesem so genannten "Mold-Verfahren" werden zunächst aufwendige Spritzgussformen hergestellt, wobei unterschiedliche Halbleiterbauteiltypen unterschiedliche Spritzgussformentwicklungen erfordern. Die relativ abrasive Kunststoffmasse beschädigt diese Spritzgussformen, sodass die Spritzgussformen häufig zu erneuern sind. Außerdem werden die elektrischen Verbindungselemente zwischen der Verdrahtungsstruktur und dem Halbleiterchip mechanisch beim Spritzgießen stark belastet, da sich die Kunststoffmasse in horizontaler Richtung aus Einspritzkanälen mit hoher Fließgeschwindigkeit in den Spritzgussformen ausbreitet, sodass die Verdrahtungselemente einer hohen Abrissgefahr ausgesetzt sind.at In a first method, the components are compounded with a molding compound envelops. In this so-called "mold process" are initially consuming Injection molds produced, with different semiconductor device types require different injection mold developments. The relative abrasive plastic mass damaged these injection molds, so the injection molds frequently too renew. Furthermore become the electrical connection elements between the wiring structure and the semiconductor chip mechanically heavily loaded during injection molding, since the plastic mass in the horizontal direction from injection channels with high flow rate spreads in the injection molds, so that the wiring elements are exposed to a high risk of demolition.
Darüber hinaus sind die Kunststoffmassen nicht universell einsetzbar, sodass jeder Bauteiltyp eine spezielle Kunststoffmischung als Spritzgussmasse erfordert.Furthermore The plastic materials are not universally applicable, so that everyone Component type a special plastic mixture as an injection molding compound requires.
Ein zweites bekanntes Verfahren, die Bauteilkomponenten der Halbleiterbauteile in eine Kunststoffmasse einzubetten, besteht darin, die Komponenten mit einem Flüssigharz zu umhüllen. Dieses Verfahren, das auch "Globe-Top-Verfahren" genannt wird, umfasst ein kostenintensives, langsames Verfahren mit quantitativ schlechteren Ergebnissen, als das "Mold-Verfahren". Ein weiterer Nachteil der bekannten, oben genannten Verfahren ist es, dass ein erheblicher Sicherheitsabstand zwischen dem Halbleiterchip und der Oberseite des Kunststoffgehäuses einzuhalten ist, um schonend das Umhüllen der Komponenten zu gewährleisten.One second known method, the component components of the semiconductor devices to embed in a plastic mass, is the components with a liquid resin to envelop. This method, which is also called "globe-top method" includes a costly, slow process with quantitatively worse ones Results, as the "mold process". Another disadvantage The known, above-mentioned method is that a considerable Safety distance between the semiconductor chip and the top to comply with the plastic housing is to gently cover the envelope to ensure the components.
Aufgabe der Erfindung ist es, ein Halbleiterbauteil mit Kunststoffgehäuse und ein Verfahren zur Herstellung desselben anzugeben, das eine kostengünstige Massenproduktion ermöglicht, und das ein flaches, Raum sparendes Kunststoffgehäuse realisiert.task The invention is a semiconductor device with plastic housing and to provide a method of producing the same, which is a cost-effective mass production allows and realized a flat, space-saving plastic housing.
Gelöst wird diese Aufgabe mit dem Gegenstand der unabhängigen Ansprüche. Vorteilhafte Weiterbildungen der Erfindung ergeben sich aus den abhängigen Ansprüchen.Is solved this object with the subject of the independent claims. Advantageous developments The invention will become apparent from the dependent claims.
Erfindungsgemäß wird ein Halbleiterbauteil mit Kunststoffgehäuse und mit zumindest einem Halbleiterchip geschaffen. Der Halbleiterchip ist auf einer Montageseite eines Systemträgers angeordnet. Dazu weist der Systemträger eine Verdrahtungsstruktur auf, die über elektrische Verbindungselemente mit dem Halbleiterchip mechanisch und elektrisch in Verbindung steht. Das Kunststoffgehäuse weist eine auflaminierte, einge ebnete, thermoplastische Kunststoffmasse auf. Diese thermoplastische Kunststoffmasse umgibt den Halbleiterchip und die Verbindungselemente zu der Verdrahtungsstruktur des Systemträgers. Außerdem bedeckt die Kunststoffmasse die Montageseite des Systemträgers derart, dass die Unterseite des Systemträgers gleichzeitig Unterseite des Halbleiterbauteils ist.According to the invention is a Semiconductor component with plastic housing and with at least one semiconductor chip created. The semiconductor chip is on a mounting side of a leadframe arranged. For this purpose, the system carrier has a wiring structure on that over electrical connection elements with the semiconductor chip mechanically and electrically connected. The plastic housing has a laminated, leveled, thermoplastic plastic compound on. This thermoplastic polymer compound surrounds the semiconductor chip and the connecting elements to the wiring structure of the system carrier. Also covered the plastic mass the mounting side of the system carrier so, that the bottom of the system tray at the same time underside of the semiconductor device is.
Dieses Halbleiterbauteil hat den Vorteil, dass es aus einem Laminat besteht, das lediglich zwei Schichten mit dazwischen angeordneten Halbleiterbauteilkomponenten aufweist. Die eine Schicht bildet den Systemträger mit seiner Montagefläche für die Halbleiterbauteilkomponenten, und die zweite Laminatschicht bildet die eingeebnete thermoplastische Kunststoffmasse. Ein derartiges Laminat als Kunststoffgehäuse hat darüber hinaus den Vorteil, dass die Verbindungselemente beim Laminieren kaum belastet werden, zumal die zu laminierende thermoplastische Kunststoffmasse die Halbleiterbauteilkomponenten ohne größere Krafteinwirkung auf die Halbleiterkomponenten umhüllt. Beim Auflaminieren wirkt nämlich der thermoplastische Kunststoff lediglich in vertikaler Richtung auf einer kurzen Distanz auf die Halbleiterkomponenten ein.This Semiconductor device has the advantage that it consists of a laminate, the only two layers with semiconductor device components arranged therebetween having. The one layer forms the system carrier with its mounting surface for the semiconductor device components, and the second laminate layer forms the leveled thermoplastic resin composition. Such a laminate as a plastic housing has the additional advantage that the fasteners are hardly loaded during lamination, especially the thermoplastic resin composition to be laminated the semiconductor device components without greater force wrapped on the semiconductor components. When lamination acts namely the thermoplastic only in the vertical direction a short distance to the semiconductor components.
Das erfindungsgemäße Halbleiterbauteil hat den weiteren Vorteil, dass keine Hohlräume zwischen der auflaminierten thermoplastischen Kunststoffmasse und dem Halbleiterbauteilkomponenten tragenden Systemträger auftreten. Ein weiterer Vorteil des Halbleiterbauteils besteht darin, dass seine Oberfläche vollkommen eben und glatt gestaltet ist, und die Dicke des Halbleiterbauteils minimiert ist, zumal weder Einlaufkanäle noch Formwerkzeuge noch Spritzgussmaschinen beim Laminiervorgang vorzusehen sind.The inventive semiconductor device has the further advantage that no voids between the laminated thermoplastic plastic material and the semiconductor device components bearing system support occur. Another advantage of the semiconductor device is that its surface is perfectly flat and smooth, and the thickness of the semiconductor device is minimized, especially since neither inlet channels still molding tools or injection molding machines are to be provided during the lamination process.
In einer bevorzugten Ausführungsform der Erfindung weisen die elektrischen Verbindungselemente zwischen Halbleiterchip und Systemträger Bonddrähte auf. Während bei der bekannten "Mold-Technik" eine enorme Belastung derartiger Bonddrähte auftritt, weil das Moldmaterial von einem vordersten Bonddraht bis zu einem hintersten Bonddraht durch das formgebende Werkzeug strömen muss, wird beim Laminieren die thermoplastische Kunststoffmasse als Folie auf den Substratträger aufgelegt und somit ein schonendes Vorgehen für das Umhüllen der empfindlichen Bondverbindungen geschaffen. Im Prinzip treten nur milde vertikale Fließrichtungen auf, die bei der Dicke d des Halbleiterchips äußerst begrenzt sind, während bei dem bekannten "Mold-Verfahren" massive Kunststoffströme vom Eingangskanal quer zu den Bonddrähten, von dem vordersten Bonddraht bis zum hintersten Bonddraht, strömen müssen.In a preferred embodiment of the invention, the electrical connection elements between Semiconductor chip and system carrier bonding wires on. While in the known "mold technique" an enormous burden such bonding wires occurs because the mold material from a foremost bonding wire up must flow to a rearmost bonding wire through the forming tool, When laminating the thermoplastic mass is a foil on the substrate carrier applied and thus a gentle procedure for the wrapping of the sensitive bonds created. In principle, only mild vertical flow directions occur which are extremely limited in the thickness d of the semiconductor chip, while at the well-known "mold process" massive plastic streams from the input channel transverse to the bonding wires, from the foremost bonding wire to the rearmost bonding wire.
In einer weiteren Ausbildung der Erfindung weisen die elektrischen Verbindungselemente zwischen Halbleiterchip und Systemträger Metallklammern auf. Derartige Metallklammern erstrecken sich von Kontaktflächen auf der aktiven Oberseite der Halbleiterchips über die Ränder der Halbleiterchips, bis zu entsprechenden Bondflächen der Verdrahtungsstruktur des Systemträgers. Das Material dieser Kontaktklammern kann ein galvanisch abgeschiedenes Metall sein, oder es können diskrete Klammerelemente zwischen den Kontaktflächen des Halbleiterchips und den Kontaktanschlussflächen des Systemträgers angeordnet sein. Die galvanisch abgeschiedenen Metallklammern haben den Vorteil, dass sie eng an dem Halbleiterchip und auf der Oberseite des Systemträgers anliegen und damit eine robuste elektrische Verbindung zwischen dem Halbleiterchip und der Verdrahtungsstruktur des Systemträgers schaffen.In Another embodiment of the invention, the electrical Connecting elements between semiconductor chip and system carrier metal brackets on. Such metal clips extend from contact surfaces the active top of the semiconductor chips over the edges of the semiconductor chips, until to corresponding bonding surfaces the wiring structure of the system carrier. The material of these contact clips can be an electrodeposited metal, or it can be discrete Clamping elements between the contact surfaces of the semiconductor chip and the contact pads of the system carrier be arranged. The galvanically deposited metal clips have the advantage of being close to the semiconductor chip and on top of the system carrier abut and thus a robust electrical connection between create the semiconductor chip and the wiring structure of the system carrier.
Darüber hinaus haben derartige Metallklammern den Vorteil, dass sie eine minimale Höhe des Halbleiterbauteils ermöglichen, zumal bei ihnen der Bonddrahtbogen üblicher Bonddrahtverbindungen entfällt. Werden diskrete Klammerelemente eingesetzt, so können diese in entsprechenden Durchgangslöchern des Systemträgers verankert sein. Diese Metallklammern können auf dem Chip und den Systemträgern gelötet oder leitfähig geklebt sein.Furthermore Such metal clips have the advantage that they have a minimal Height of the semiconductor device enable, especially with them the bonding wire arch of conventional bonding wire connections is eliminated. Become Discrete clip elements used, so they can in appropriate Through holes of the system carrier be anchored. These metal clips can be soldered on the chip and the system carriers or conductive be glued.
Ein weiteres elektrisches Verbindungselement zwischen Halbleiterchip und Systemträger bilden Flipchip-Kontakte. Solche Flipchip-Kontakte sind als Lotkugeln auf entsprechenden Kontaktflächen der aktiven Oberseite eines Halbleiterchips angeordnet und können auf der gesamten Oberseite des Halbleiterchips verteilt sein. Üblicherweise konzentrieren sich diese Lotkugeln jedoch an den Randbereichen des Halbleiterchips. Der Vorteil dieser Verbindungselemente ist, dass weder eine Klammer noch ein Bonddraht die Dicke des Halbleiterbauteils bestimmen. Jedoch können die Flipchip-Kontakte nicht beliebig klein hergestellt werden, sodass sich ein Zwischenraum zwischen der Oberseite des Systemträgers und der aktiven Oberseite des Halbleiterchips ausbildet. Dieser Zwischenraum stellt eine Übergangszone dar, in der sich die Unterschiede im thermischen Ausdehnungskoeffizienten zwischen Halbleiterchip, der üblicherweise aus einem monokristallinen Silicium besteht, und dem Trägersubstrat bzw. Systemträgerstreifen, der glasfaserverstärktes Epoxydharz aufweisen kann, ausgleichen sollen.One another electrical connection element between the semiconductor chip and system carriers form flip-chip contacts. Such flip-chip contacts are as solder balls on corresponding contact surfaces of the active top of a semiconductor chip and can be placed on be distributed over the entire top of the semiconductor chip. Usually However, these solder balls concentrate on the edge areas of the Semiconductor chips. The advantage of these fasteners is that neither a clamp nor a bonding wire the thickness of the semiconductor device determine. However, you can the flipchip contacts are not made arbitrarily small, so There is a gap between the top of the system carrier and forms the active top of the semiconductor chip. This gap represents a transition zone in which the differences in the thermal expansion coefficient between semiconductor chip, usually consists of a monocrystalline silicon, and the carrier substrate or system carrier strip, the glass fiber reinforced Epoxy resin may have to balance.
Bei hoher thermischer Belastung können die Unterschiede in den thermischen Ausdehnungskoeffizienten zwischen Silicium und Epoxydharz zu Kontaktabrissen führen. Um die Verbindung zwischen Halbleiterchip und Systemträger mechanisch zu ver festigen, wird deshalb in einer bevorzugten Ausführungsform der Erfindung dieser Zwischenraum zwischen den Flipchip-Kontakten der Oberseite des Halbleiterchips und der Oberseite des Systemträgers mit einem gefüllten Kunststoff aufgefüllt. Dabei ist der polymere Kunststoff durch keramische Kunststoffpartikel derart aufgefüllt, dass er einen Übergang im thermischen Verhalten zwischen Halbleiterchipmaterial und Systemträgermaterial vermittelt.at high thermal load can the differences in the thermal expansion coefficient between Silicon and epoxy lead to contact breaks. To connect the semiconductor chip and system carriers mechanically consolidate ver, is therefore in a preferred embodiment the invention of this gap between the flip-chip contacts of the top of the semiconductor chip and the top of the system carrier with a filled one Plastic filled up. Here, the polymeric plastic is by ceramic plastic particles so filled up, that he has a transition in the thermal behavior between semiconductor chip material and system carrier material taught.
Im Falle von Bonddrahtverbindungen oder Klammerverbindungen ist der Halbleiterchip mit seiner Rückseite stoffschlüssig mit dem Systemträger verbunden. Diese stoffschlüssige Verbindung sorgt dafür, dass beim Anschließen der Verbindungselemente, sei es der Metallklammern oder der Bonddrähte, der Halbleiterchip bereits fixiert ist, sodass eine sichere Handhabung der Verbindungstechniken stattfinden kann. Die stoffschlüssige Verbindung selbst kann eine Klebstoffverbindung darstellen, oder eine eutektische Lötverbindung, oder speziell eine Diffusionslötverbindung mit entsprechenden intermetallischen Phasen aufweisen. Auch mithilfe von Lotpasten können die stoffschlüssigen Verbindungen zwischen Halbleiterchip und Verdrahtungsstruktur hergestellt werden. Für eine elektrische Verbindung sind neben den metallischen Lotverbindungen auch Klebstoffe geeignet, die leitfähige Partikel als Füllmaterial aufweisen. Derartige Klebstoffe werden auch "Leitkleber" genannt.in the Trap of bonding wire connections or clip connections is the Semiconductor chip with its backside cohesively connected to the system carrier. This cohesive Connection ensures that when connecting the fasteners, be it the metal brackets or the bonding wires, the Semiconductor chip is already fixed, so safe handling the joining techniques can take place. The cohesive connection itself may be an adhesive compound, or an eutectic soldered connection, or especially a diffusion solder joint having corresponding intermetallic phases. Also using of solder paste can the cohesive Connections made between semiconductor chip and wiring structure become. For an electrical connection are in addition to the metallic solder joints also suitable adhesives, the conductive particles as filler exhibit. Such adhesives are also called "conductive adhesives".
Ein Verfahren zur Herstellung eines Halbleiterbauteils mit Kunststoffgehäuse und mit einem Halbleiterchip, der auf einer Montageseite eines Systemträgers montiert ist, weist die nachfolgenden Verfahrensschritte auf. Zunächst wird eine thermoplastische Folie hergestellt, deren Dicke D mindestens der Dicke d eines einzubettenden Halbleiterchips mit zugehö rigen elektrischen Verbindungselementen entspricht. Parallel dazu kann das Herstellen eines Systemträgerstreifens erfolgen. Dieser Systemträgerstreifen weist mehrere Halbleiterbauteilpositionen auf. Auf der Montageseite des Systemträgerstreifens wird eine Verdrahtungsstruktur für jede der Halbleiterbauteilpositionen aufgebracht.A method for manufacturing a semiconductor device with a plastic housing and with a semiconductor chip, which is mounted on a mounting side of a system carrier, comprises the following method steps. First, a thermoplastic film is produced whose thickness D corresponds to at least the thickness d of a semiconductor chip to be embedded with zugehö ring electrical connection elements. Parallel to this, the production of a system carrier strip can take place. This system carrier strip has a plurality of semiconductor device positions on. On the mounting side of the leadframe, a wiring pattern is deposited for each of the semiconductor device positions.
Derartige Verdrahtungsstrukturen können Durchkontakte von der Montageseite des Systemträgers zur gegenüberliegenden Unterseite des Systemträgers aufweisen. Außerdem weist die Verdrahtungsstruktur Bondflächen für die Halbleiterchips auf, um diese elektrisch über entsprechende Verbindungselemente mit der Verdrahtungsstruktur verbinden zu können. Die Anordnung der Bondflächen und die Größe der Bondflächen hängt von den aufzubringenden Verbindungselementen ab, was später erörtert wird. Nachdem die Halbleiterchips mit der Verdrahtungsstruktur über die Verbindungselemente verbunden sind, wird die thermoplastische Folie, unter Abdecken und Einbetten der Verdrahtungsstruktur, der Halbleiterchips und der elektrischen Verbindungselemente in den Halbleiterbauteilpositionen auf die Montageseite des Systemträgerstreifens auflaminiert. Anschließend wird der Systemträgerstreifen in einzelne Halbleiterbauteile aufgetrennt.such Wiring structures can vias from the mounting side of the system carrier to the opposite Bottom of the system carrier exhibit. Furthermore the wiring structure has bonding pads for the semiconductor chips to these electrically over connect corresponding connecting elements with the wiring structure to be able to. The arrangement of the bonding surfaces and the size of the bonding pads depends on the applied fasteners, which will be discussed later. After the semiconductor chips with the wiring structure over the Connecting elements are connected, the thermoplastic film, Covering and embedding the wiring structure, the semiconductor chips and the electrical connection elements in the semiconductor device positions laminated on the mounting side of the system carrier strip. Subsequently becomes the system carrier strip separated into individual semiconductor components.
Dieses Verfahren hat den Vorteil, dass mithilfe einer kostengünstigen Laminierungstechnik eine vorbereitete thermoplastische Folie auf eine Vielzahl von Halbleiterbauteilpositionen auflaminiert werden kann, sodass dieses Verfahren für eine preiswerte Massenproduktion von Halbleiterbauteilen geeignet erscheint. Ferner hat das Verfahren den Vorteil, dass durch entsprechende Maßnahmen beim Auflaminieren der thermoplastischen Folie, die Oberseite des Bauteilgehäuses trotz der ein zubettenden Halbleiterbauteilkomponenten vollständig eben dargestellt werden kann.This Procedure has the advantage of using a cost-effective Lamination technology on a prepared thermoplastic film a plurality of semiconductor device positions can be laminated, so this procedure for an inexpensive mass production of semiconductor devices seems suitable. Furthermore, the method has the advantage that by appropriate measures when laminating the thermoplastic film, the top of the component housing despite the semiconductor component components to be embedded are completely flat can be represented.
Um den Halbleiterchip elektrisch mit dem Substratträgerstreifen bzw. mit der darauf befindlichen Verdrahtungsstruktur zu verbinden, wird in einer bevorzugten Durchführungsform des Verfahrens zunächst die Rückseite des Halbleiterchips stoffschlüssig mit der Verdrahtungsstruktur verbunden. Um gleichzeitig eine elektrische Verbindung mit der Verdrahtungsstruktur herzustellen, kann als stoffschlüssiges Verfahren ein eutektisches Lot auf die Verdrahtungsstruktur im Bereich der Bondfläche und/oder auf die Rückseite des Halbleiterchips aufgebracht werden.Around the semiconductor chip electrically with the substrate carrier strip or with the on it to connect the underlying wiring structure is in a preferred Implementing form the procedure first the backside the semiconductor chip cohesively connected to the wiring structure. At the same time an electric Making connection with the wiring structure, as a cohesive process a eutectic solder on the wiring structure in the area of Bonding surface and / or on the back of the semiconductor chip are applied.
Ferner besteht die Möglichkeit, auf die Rückseite des Halbleiterchips, sowie auf die Bondfläche der Verdrahtungsstruktur Komponenten für ein Diffusionslöten aufzubringen, die bei niedriger Löttemperatur hochschmelzende intermetallische Verbindungen bilden. Ferner ist es auch möglich, wenn eine elektrische Verbindung gleichzeitig mit dem Befestigen des Halbleiterchips auf der Verdrahtungsstruktur durchgeführt werden soll, einen Leitkleber einzusetzen, der entsprechende leitfähige Partikel aufweist. Nachdem auf diese Weise der Halbleiterchip stoffschlüssig und mechanisch fest mit der Verdrahtungsstruktur verbunden ist, werden die elektrischen Verbindungselemente in Form von Bonddrähten auf Kontaktflächen der aktiven Oberseite des Halbleiterchips und auf Bondflächen der Verdrahtungsstruktur gebondet. Zu diesem Zweck werden als Bonddrähte Aluminium- oder Golddrähte eingesetzt, und die entsprechenden Kontaktflächen mit Gold bzw. Aluminium beschichtet, da die Kombination Gold auf Aluminium eine eutektische, niedrig schmelzende Verbindung eingeht, und somit den Bondvorgang unterstützt.Further it is possible, on the back of the semiconductor chip, as well as on the bonding surface of the wiring structure Components for a diffusion soldering apply, the high melting at low soldering temperature form intermetallic compounds. Furthermore, it is also possible if an electrical connection simultaneously with the attachment of the Semiconductor chips are performed on the wiring structure is to use a conductive adhesive, the corresponding conductive particles having. After in this way, the semiconductor chip cohesively and mechanically firmly connected to the wiring structure are the electrical connection elements in the form of bonding wires on contact surfaces of active top of the semiconductor chip and bonding surfaces of the Wiring structure bonded. For this purpose, the bonding wires used are aluminum or gold wires used, and the corresponding contact surfaces with gold or aluminum because the combination of gold and aluminum is eutectic, low-melting compound enters, and thus the bonding process supported.
Anstelle von Bonddrähten können als elektrische Verbindungselemente auch Metallklammern vorgesehen werden, die zwischen Kontaktflächen der aktiven Oberseite des Halbleiterchips und Bondflächen der Verdrahtungsstruktur fixiert werden. Dieses Fixieren kann einerseits durch Abscheiden von entsprechenden Metalllegierungen mit anschließender Strukturierung erfolgen, sodass sich eng anliegende Klammern von den Kontaktflächen des Halbleiterchips über die Randbereiche des Halbleiterchips und über die Oberseite des Systemträgerstreifens bis hin zu entsprechenden Durchkontakten im Systemträgerstreifen erstrecken. Andererseits sind auch elektrisch leitende mechanische Klammern denkbar, die in den Durchkontaktöffnungen des Systemträgers verankert sind und allein mit mechanischem Druck die Kontaktflächen des Halbleiterchips kontaktieren. Eine Verbindung kann auch über Löten oder Leitkleben erfolgen.Instead of of bonding wires can provided as electrical fasteners and metal brackets be that between contact surfaces of the active top side of the semiconductor chip and bonding surfaces of the wiring structure be fixed. This fixation can on the one hand by deposition of corresponding metal alloys with subsequent structuring be made so that close-fitting brackets from the contact surfaces of Semiconductor chips over the edge regions of the semiconductor chip and over the top of the system carrier strip up to corresponding through contacts in the system carrier strip extend. On the other hand, electrically conductive mechanical Brackets conceivable that anchored in the through holes of the system carrier are and only with mechanical pressure the contact surfaces of the Contact semiconductor chips. A connection can also about soldering or Conductive bonding done.
Bei einer dritten Ausführungsform des elektrischen Verbindens zwischen der Verdrahtungsstruktur des Systemträgers und den Kontaktflächen des Halbleiterchips werden Flipchip-Kontakte eingesetzt, die auf entsprechende Kontaktflächen der aktiven Oberseite des Halbleiterchips gelötet sind. In diesem Fall ist die Rückseite des Halbleiterchips nicht stoffschlüssig mit der Verdrahtungsstruktur verbunden, sondern die Flipchip-Kontakte werden unmittelbar auf entsprechende Bondflächen der Verdrahtungsstruktur fixiert, sodass weder Bonddrähte noch Metallklammern erforderlich sind, um die elektrische Verbindung zwischen Halbleiterchip und Verdrahtungsstruktur herzustellen. In diesem Fall entsteht ein Zwischenraum, der einerseits die Dicke des Halbleiterbauteils erhöht und andererseits durch einen entsprechenden "Underfill" aufgefüllt werden muss, um die thermischen Spannungen zwischen dem Systemträgermaterial und dem Halbleitermaterial auszugleichen.at a third embodiment the electrical connection between the wiring structure of the leadframe and the contact surfaces of the Semiconductor chips flip-chip contacts are used, which are based on appropriate contact surfaces the active top of the semiconductor chip are soldered. In this case is the backside of the semiconductor chip not materially connected to the wiring structure but the flip-chip contacts are applied directly to corresponding bond pads of the wiring structure fixed so that neither bonding wires Still metal clips are required to make the electrical connection between the semiconductor chip and the wiring structure. In In this case creates a gap, on the one hand, the thickness of the semiconductor device increases and on the other hand by a corresponding "underfill" must be filled to the thermal Tensions between the system carrier material and compensate for the semiconductor material.
Bei einer weiteren Durchführung des Verfahrens werden die thermoplastische Folie und/oder der Systemträgerstreifen für ein Aufbringen der thermoplastischen Folie auf den Systemträgerstreifen erwärmt. Diese Erwärmung kann bis zum unteren Erweichungspunkt des thermoplastischen Materials durchgeführt werden, bei dem das thermoplastische Material noch zäh viskos ist, und beim Aufbringen auf den Systemträger mit den darauf befindlichen Halbleiterbauteilkomponenten diese derart einbettet, dass auf der Oberseite der Folie eine ebene Oberseite bestehen bleibt.In a further implementation of the method, the thermoplastic film and / or the system carrier strip are heated for application of the thermoplastic film to the system carrier strip. This warming can be up to the lower he be performed soft point of the thermoplastic material in which the thermoplastic material is still viscous viscous, and when applied to the leadframe with the semiconductor device components thereon embedding them such that on the top of the film remains a flat top.
Um diese Ebenheit zu perfektionieren und auch um Lufteinschlüsse zu vermeiden, wird zum Auflaminieren der thermoplastischen Folie auf die Montageseite des Systemträgerstreifens, die Folie und der Systemträgerstreifen unter einer Andruckwalze durchgeführt. Diese Andruckwalze sorgt für ein Einebnen der Kunststofffolie, sodass eine vollständig planare Oberseite auf dem Systemträger entsteht. Vor einem Auftrennen des Systemträgerstreifens in einzelne Halbleiterbauteile können in einer weiteren Ausführungsform der Erfindung auf der Unterseite des Systemträgers Außenkontaktflächen oder Außenkontakte angeordnet werden. Dazu können Außenkontaktkugeln aus Lotmaterial oder flächige Lotbeschichtungen auf die Flächen der Durchkontakte auf der Unterseite des Systemträgerstreifens aufgebracht werden. Dieses hat den Vorteil, dass das Aufbringen von Außenkontakten großflächig und gleichzeitig für viele Halbleiterbauteile erfolgen kann, was die Prozesskosten vermindert.Around to perfect this flatness and also to avoid air pockets, is used to laminate the thermoplastic film to the mounting side of the system carrier strip, the film and the system carrier strip performed under a pressure roller. This pressure roller ensures for a leveling the plastic film, leaving a completely planar top on the system carrier arises. Before splitting the system carrier strip into individual semiconductor components can in a further embodiment the invention on the underside of the system carrier external contact surfaces or external contacts to be ordered. Can do this External contact balls made of solder or flat Lot coatings on the surfaces the vias on the bottom of the system carrier strip be applied. This has the advantage that the application from external contacts large area and at the same time for Many semiconductor devices can be done, which reduces the process costs.
Zusammenfassend ist festzustellen, dass mit einem Laminierungsprozess eines thermoplastischen Materials die bereits kontaktierten Chips ein einfaches, preiswertes Verfahren zur Verfügung steht, mit dem eine große Zahl von Halbleiterbauteilen preiswert hergestellt werden kann. Dieser Prozess kann zum Erzielen niedrigerer Viskositäten und für eine verbesserte Penetration des thermoplastischen Materials auf den Komponenten des Halbleiterbauteils auch bei höheren Temperaturen erfolgen. Eine höhere Temperatur kann beispielsweise mittels eines Heizluftstromes aufgebracht werden, der gleichzeitig einen leichten Druck auf den Thermoplasten und auf den Chipträger ausübt. Wird der Chipträger mit der thermoplastischen Folie mithilfe einer Andruckwalze verbunden, so ist es von Vorteil, vor dem Laminieren eine Kunststoffschutzfolie auf das thermoplastische Material aufzubringen, um ein Kleben und Anbacken des thermoplastischen Materials an der Walzenoberfläche zu vermeiden. Mit dem erfindungsgemäßen Verfahren können zusammenfassend die folgenden Vorteile erreicht werden:
- 1. sehr dünne Bauelemente sind realisierbar;
- 2. eine geringe Drahtverwehung aufgrund minimaler Strömung des Laminats quer zum Draht (im Gegensatz zum Drahtbonden) ist erreichbar;
- 3. die Bauteilhöhe kann durch die Verbindungstechnik vermindert werden (beim Drahtbonden durch die Drahtbondschleife, bei der Flipchip-Technik durch die Flipchip-Kontakthöhe);
- 4. der Umhüllungsprozess kann für beliebig große Nutzen durchgeführt werden;
- 5. billigere Materialien in Form dieser Thermoplaste sind einsetzbar;
- 6. das Umhüllmaterial kann aufgrund der thermoplastischen Eigenschaften recycled werden;
- 7. eine einfache Kontrolle der mechanischen Eigenschaften des Umhüllmaterials ist möglich, da prinzipiell alle Thermoplaste für die erfindungsgemäßen Bauelemente und das erfindungsgemäße Verfahren geeignet sind;
- 8. keine speziellen Anforderungen werden an das Unhüllmaterial gestellt (im Gegensatz zum "Underfill"-Material bei der Flipchip-Technik).
- 1. very thin components can be realized;
- 2. low wire drift due to minimal flow of the laminate across the wire (as opposed to wire bonding) is achievable;
- 3. The component height can be reduced by the connection technique (wire bonding by the wire bond loop, in flip chip technology by the flip chip contact height);
- 4. the wrapping process can be carried out for any size of benefit;
- 5. cheaper materials in the form of these thermoplastics can be used;
- 6. the wrapping material can be recycled due to the thermoplastic properties;
- 7. a simple control of the mechanical properties of the wrapping material is possible, since in principle all thermoplastics are suitable for the components of the invention and the inventive method;
- 8. No special requirements are made on the non-wrapping material (in contrast to the "underfill" material in flip-chip technology).
Somit wird durch die Erfindung die Herstellung sehr dünner Gehäuse mittels spezifischer Materialien und der oben aufgeführten Prozesse realisierbar.Consequently By the invention, the production of very thin housing by means of specific materials and the one listed above Processes feasible.
Die Erfindung wird nun anhand der beigefügten Figuren näher erläutert.The The invention will now be described with reference to the accompanying figures.
Wie
Die
ursprüngliche
Dicke der thermoplastischen Folie
Die
strichpunktierten Linien
Ein
Zwischenraum
- 11
- KunststoffgehäusePlastic housing
- 22
- HalbleiterchipSemiconductor chip
- 33
- Montageseite des Systemträgersmounting side of the system carrier
- 44
- Systemträger bzw. SystemträgerstreifenSystem carrier or System carrier strip
- 55
- Verdrahtungsstrukturwiring structure
- 66
- elektrisches Verbindungselementelectrical connecting element
- 77
- thermoplastische Kunststoffmassethermoplastic Plastic compound
- 88th
- Bonddrahtbonding wire
- 99
- Metallklammermetal clip
- 1010
- HalbleiterbauteilSemiconductor device
- 1111
- Flipchip-KontaktFlip-Contact
- 1212
- thermoplastische Foliethermoplastic foil
- 1313
- HalbleiterbauteilpositionSemiconductor component position
- 1414
- Rückseite des Halbleiterchipsback of the semiconductor chip
- 1515
- Kontaktfläche des HalbleiterchipsContact surface of the Semiconductor chips
- 1616
- Oberseite des Halbleiterchipstop of the semiconductor chip
- 1717
- Bondfläche der VerdrahtungsstrukturBonding surface of wiring structure
- 1818
- Zwischenraumgap
- 1919
- Oberseite der Halbleiterbauteilpositiontop the semiconductor device position
- 2020
- Halbleiterbauteil (zweite Ausführungsform)Semiconductor device (second embodiment)
- 2121
- Füllmaterialfilling material
- 2222
- Oberseite der thermoplastischen Folietop the thermoplastic film
- 2323
- Außenkontakte des Halbleiterbauteilsexternal contacts of the semiconductor device
- 2424
- Andruckwalzepressure roller
- 2525
- Unterseite des Systemträgersbottom of the system carrier
- 2626
- Durchkontaktby contact
- 2727
- strichpunktierte Liniedot-dash line
- 3030
- Halbleiterbauteil (dritte Ausführungsform)Semiconductor device Third Embodiment
- AA
- Pfeilrichtungarrow
- BB
- Pfeilrichtungarrow
- CC
- Pfeilrichtungarrow
- Ee
- Pfeilrichtungarrow
- DD
- Dicke der thermoplastischen Foliethickness the thermoplastic film
- dd
- Dicke eines einzubettenden Halbleiterchips mit Verbinthickness of a semiconductor chip to be embedded with verbin
- dungenfertilize
Claims (17)
Priority Applications (2)
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DE102004027787A DE102004027787A1 (en) | 2004-06-08 | 2004-06-08 | Semiconductor devices with plastic housing and method of making the same |
PCT/DE2005/001003 WO2005122248A1 (en) | 2004-06-08 | 2005-06-06 | Semiconductor components having a plastic housing, and method for the production thereof |
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DE102004027787A DE102004027787A1 (en) | 2004-06-08 | 2004-06-08 | Semiconductor devices with plastic housing and method of making the same |
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DE102004027787A1 true DE102004027787A1 (en) | 2006-01-05 |
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DE102019121012A1 (en) * | 2019-08-02 | 2021-02-04 | Infineon Technologies Ag | Encapsulated package with carrier, laminate body and component in between |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19525933A1 (en) * | 1995-07-17 | 1997-01-23 | Finn David | IC card module and method and device for its production |
WO1998016901A1 (en) * | 1996-10-14 | 1998-04-23 | Zakel, Elke | Method for the manufacture of a contactless smart card |
EP1095386B1 (en) * | 1998-06-18 | 2004-03-03 | Stichting Energieonderzoek Centrum Nederland(ECN) | Method for manufacturing a photovoltaic element containing a liquid electrolyte |
US20040089408A1 (en) * | 2001-04-25 | 2004-05-13 | Volker Brod | Method for connecting microchips to an antenna arranged on a support strip for producing a transponder |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5148265A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
JP3378338B2 (en) * | 1994-03-01 | 2003-02-17 | 新光電気工業株式会社 | Semiconductor integrated circuit device |
US6885101B2 (en) * | 2002-08-29 | 2005-04-26 | Micron Technology, Inc. | Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods |
-
2004
- 2004-06-08 DE DE102004027787A patent/DE102004027787A1/en not_active Withdrawn
-
2005
- 2005-06-06 WO PCT/DE2005/001003 patent/WO2005122248A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19525933A1 (en) * | 1995-07-17 | 1997-01-23 | Finn David | IC card module and method and device for its production |
WO1998016901A1 (en) * | 1996-10-14 | 1998-04-23 | Zakel, Elke | Method for the manufacture of a contactless smart card |
EP1095386B1 (en) * | 1998-06-18 | 2004-03-03 | Stichting Energieonderzoek Centrum Nederland(ECN) | Method for manufacturing a photovoltaic element containing a liquid electrolyte |
US20040089408A1 (en) * | 2001-04-25 | 2004-05-13 | Volker Brod | Method for connecting microchips to an antenna arranged on a support strip for producing a transponder |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102019121012A1 (en) * | 2019-08-02 | 2021-02-04 | Infineon Technologies Ag | Encapsulated package with carrier, laminate body and component in between |
DE102019121012B4 (en) | 2019-08-02 | 2024-06-13 | Infineon Technologies Ag | Package and method for producing a package |
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