DE102004023752B4 - Method for avoiding the reduction of the thickness of the rewiring - Google Patents
Method for avoiding the reduction of the thickness of the rewiring Download PDFInfo
- Publication number
- DE102004023752B4 DE102004023752B4 DE200410023752 DE102004023752A DE102004023752B4 DE 102004023752 B4 DE102004023752 B4 DE 102004023752B4 DE 200410023752 DE200410023752 DE 200410023752 DE 102004023752 A DE102004023752 A DE 102004023752A DE 102004023752 B4 DE102004023752 B4 DE 102004023752B4
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- Prior art keywords
- layer
- rewiring
- resist
- seed
- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Abstract
Verfahren
zur Vermeidung der Verringerung der Dicke der Um verdrahtung beim
Seed-Layer-Ätzen,
bei dem zunächst
auf der Passivierung einer fertiggestellten Halbleiteranordnung
eine Seed-Layer ganzflächig abgeschieden
wird, indem zunächst
eine Ti-Schicht und darüber
eine Cu-Schicht durch Sputtern abgeschieden werden, anschließend ein
Resist ganzflächig
auf die Seed-Layer aufgetragen wird und danach die Umverdrahtung
durch photolithographische Strukturierung des Resists mit nachfolgendem
Cu-Plating hergestellt wird, indem die im Resist photolithographisch
ausgebildeten Gräben mit
Cu ausgefüllt
werden, wobei
– genau
eine aus einem Metall bestehende Opferschicht (6) ganzflächig auf
der Resistmaske (5) und unmittelbar auf der Umverdrahtung (4) als
nächste
Schicht zum Schutz der darunter liegenden mittels Cu-Plating hergestellten
Umverdrahtung (4) abgeschieden wird,
– die Opferschicht (6) eine
Metallschicht mit größerer Dichte
und/oder höherem Ätzwiderstand
als die mittels Cu-Plating hergestellte Schicht der Umverdrahtung
(4) ist,
– die
Opferschicht (6) durch Sputtern aufgetragen wird,
– die Resistmaske
(5) durch einen Lift-Off-Schritt entfernt...Method for avoiding the reduction of the thickness of the rewiring in seed-layer etching, in which first on the passivation of a finished semiconductor device, a seed layer is deposited over the entire surface by first a Ti layer and above a Cu layer are deposited by sputtering , Then, a resist over the entire surface is applied to the seed layer and then the rewiring by photolithographic patterning of the resist with subsequent Cu plating is made by the photolithographically formed in the resist trenches are filled with Cu, wherein
Exactly one sacrificial layer (6) consisting of a metal is deposited over the entire area of the resist mask (5) and directly on the rewiring (4) as the next layer for protecting the underlying rewiring (4) produced by means of Cu plating,
The sacrificial layer (6) is a metal layer with a higher density and / or higher etching resistance than the layer of the rewiring (4) produced by means of Cu plating,
The sacrificial layer (6) is applied by sputtering,
- The resist mask (5) removed by a lift-off step ...
Description
Die Erfindung betrifft ein Verfahren zur Vermeidung der Verringerung der Dicke der Umverdrahtung beim Seed-Layer-Ätzen, bei dem zunächst auf der Passivierung einer fertiggestellten Halbleiteranordnung eine Seed-Layer ganzflächig abgeschieden wird, indem zunächst eine Ti-Schicht und darüber eine Cu-Schicht durch Sputtern abgeschieden werden, anschließend ein Resist ganzflächig auf die Seed-Layer aufgetragen wird und danach die Umverdrahtung durch photolithographische Strukturierung des Resists mit nachfolgendem Cu-Plating hergestellt wird, indem die im Resist photolithographisch ausgebildeten Gräben mit Cu ausgefüllt werden.The The invention relates to a method for avoiding the reduction the thickness of the rewiring in seed layer etching, at first on the Passivation of a finished semiconductor device a seed layer the whole area is deposited by first a Ti layer and above that Cu layer through Sputtering are deposited, then a resist over the entire surface the seed layer is applied and then rewiring photolithographic structuring of the resist with following Cu plating is produced by photolithographically formed in the resist trenches filled with Cu become.
Die sogenannten Redistribution Layer (RDL) bzw. Umverdrahtungen werden verwendet, um auf der Passivierung, z.B. einer Polyimidschicht, eines fertig gestellten Halbleiterbauelementes die im allgemeinen dicht gepackten Bondpads, z.B. in einer zentralen ein- oder mehrreihigen Anordnung (center row), in eine weniger dicht gepackte Anordnung von Anschlusskontakten oder zu einer Arrayanordnung (Ball Grid array) umzuverdrahten. Derartige Reroute Layer bestehen in der Hauptsache aus einer Kupferschicht, auf der gegebenenfalls zumindest partiell eine Ni-Schicht und dann eine Au-Schicht zumindest im Kontaktbereich angeordnet ist. Die Nickelschicht dient dem Schutz der Cu-Schicht vor Korrossion. werden die Reroute-Layer als buried Layer, also als vergrabene Layer ausgebildet, die dann durch eine Passivierungsschicht, oder einen Moldcompound umhüllt werden, erübrigt sich die zusätzliche Abscheidung einer Ni-Schicht.The so-called Redistribution Layer (RDL) or rewiring used to test for passivation, e.g. a polyimide layer, a completed semiconductor device generally tightly packed bond pads, e.g. in a central single or multi-row Center row, in a less densely packed arrangement from connectors or to an array arrangement (ball grid array) rewire. Such reroute layers exist in the main from a copper layer on which optionally at least partially a Ni layer and then an Au layer at least in the contact area is arranged. The nickel layer serves to protect the Cu layer before corrosion. the reroute layers become buried layers, so formed as a buried layer, which is then passed through a passivation layer, or wrapped in a molding compound become unnecessary the extra Deposition of a Ni layer.
Um auf der obersten Schicht des Wafers/Chip, die in der Regel eine Passivierungsschicht (z.B. ein Polyimid) enthält, eine Kupferschicht entsprechend der Anordnung der gewünschten Reroute Layer erzeugen zu können, ist es zunächst unumgänglich, auf der Polyimidschicht eine sogenannte Seed-Layer herzustellen, auf der dann die Kupferschicht galvanisch abgeschieden werden kann (Cu-Plating). Um die Seed-Layer herzustellen, wird auf der Polyimidschicht zunächst eine dünne Titanschicht durch Sputtern abgeschieden und anschließend eine Cu-Schicht gesputtert.Around on the top layer of the wafer / chip, which is usually a Passivation layer (e.g., a polyimide) containing a copper layer accordingly the arrangement of the desired Reroute Layer to be able to generate it is first unavoidable to produce a so-called seed layer on the polyimide layer, on which then the copper layer can be electrodeposited (Cu-plating). To make the seed layer, a polyimide layer is first formed thin titanium layer deposited by sputtering and then sputtered a Cu layer.
Anschließend wird die eigentliche Cu-Leitbahn galvanisch abgeschieden. Um das Ausführen zu können, wird zunächst ein Resist, z.B. ein elektrophoretischer Resist, abgeschieden, der dann auf übliche Weise photolithographisch strukturiert wird, um dann in der Maske eine galvanische Abscheidung von Cu vornehmen zu können, um die gewünschte Reroute Layer auszubilden. Nach der Abscheidung des Cu wird dann der Resist entfernt, so dass die Cu-Reroute-Layer frei liegt. Anschließend muss die Seed-Layer von sämtlichen Bereichen außerhalb der Reroute-Layer entfernt werden, um z.B. Kurzschlüsse auf dem Wafer/Chip zu vermeiden.Subsequently, will the actual Cu interconnect galvanically deposited. To do this can, will be first a resist, e.g. an electrophoretic resist deposited, the then on usual Photolithographically structured, then in the mask to perform a galvanic deposition of Cu in order the desired route Form layers. After the deposition of the Cu then the resist removed so that the Cu Reroute layer is exposed. Then must the seed layer of all Areas outside the reroute layer are removed, e.g. Short circuits to avoid the wafer / chip.
Das Entfernen der Seed-Layer erfolgt durch Ätzen. Dabei entsteht das Problem, dass beim Ätzen der Seed-Layer natürlich gleichzeitig auch die galvanisch abgeschiedene (geplatete) Cu-Schicht mit geätzt wird, was zur Folge hat, dass die Reroute Layer nach dem Ätzen einen extrem reduzierten Querschnitt aufweist, was einen erheblich erhöhten Widerstand zur Folge hat. Diese nachteilige Folge des Ätzvorganges entsteht einfach dadurch, dass das Ätzen der Seed-Layer, insbesondere deren gesputterten Cu-Anteiles, wesentlich langsamer erfolgt, als das Ätzen der plattierten Cu-Schicht. Verursacht wird das offensichtlich dadurch, dass die gesputterte Cu-Schicht eine wesentlich größere Dichte aufweist, als die galvanisch abgeschiedene Cu-Schicht.The Removing the seed layer is done by etching. This creates the problem that when etching the Seed layer of course at the same time the electrodeposited (plated) Cu layer etched with This will cause the reroute layer to become one after etching having extremely reduced cross section, resulting in significantly increased resistance entails. This adverse consequence of the etching process arises easily in that the etching the seed layer, in particular their sputtered Cu content, essential slower than the etching the plated Cu layer. This is obviously caused by that the sputtered Cu layer has a much greater density has, as the electrodeposited Cu layer.
Aus
der
Zu
selbem Zweck lehrt die
Der Erfindung liegt nunmehr die Aufgabe zugrunde, die Verfahren zur Vermeidung der Verringerung der Dicke der Umverdrahtung beim Seed-Layer-Ätzen weiter zu entwickeln und prozesstechnisch zu vereinfachen.Of the Invention is now the object of the method for Avoiding the reduction in the thickness of the rewiring during seed layer etching continues to develop and simplify process technology.
Die der Erfindung zugrunde liegende Aufgabe wird bei einem Verfahren der eingangs genannten Art durch die kennzeichnenden Merkmale des unabhängigen Anspruchs gelöst.The The object underlying the invention is in a method of the type mentioned by the characterizing features of independent Claim solved.
Weitere Ausgestaltungen der Erfindung gehen aus den zugehörigen Unteransprüchen hervor.Further Embodiments of the invention will become apparent from the accompanying dependent claims.
Durch dieses Verfahren wird mit einfachen Mitteln, d.h. mit einem sehr einfachen zusätzlichen Prozessschritt, ein wirksamer Schutz der geplateten Cu-Schicht der Umverdrahtung während des Ätzens der Seed-Layer erreicht. Ein weiterer Vorteil ist darin zu sehen, dass der Ätzvorgang mit höherer Energie, höherer Konzentration und/oder Temperatur des Ätzgases und damit in kürzerer Zeit erfolgen kann und dass keine weiteren Lithographieschritte notwendig sind. Im Anschluss an das Ätzen der Seed-Layer kann dann das Halbleiterbauelement durch Molden fertig gestellt werden.By this method, an effective protection of the plated Cu layer of the rewiring during the etching of the seed layer is achieved by simple means, ie with a very simple additional process step. Another advantage is the fact that the etching process with higher energy, higher concentration and / or temperature of the etching gas and thus can be done in a shorter time and that no further lithography steps are necessary. Subsequent to the etching of the seed layer, the semiconductor component can then be finished by Molden.
Die Erfindung soll nachfolgend an einem Ausführungsbeispiel näher erläutert werden. In den zugehörigen Zeichnungen zeigen:The Invention will be explained in more detail below using an exemplary embodiment. In the associated Drawings show:
In
In
Das
besondere ist hier, dass auf der Resistmaske
Anstelle Cu können auch Au, Ti, Pt, Ta bzw. andere geeignete Metalle für die Opferschicht eingesetzt werden.Instead of Cu can also Au, Ti, Pt, Ta or other suitable metals for the sacrificial layer be used.
Die
an sich unnötige
Opferschicht
Das
Ergebnis des Lift-Off Prozesses ist in
- 11
- Passivierungsschichtpassivation
- 22
- Ti-SchichtTi layer
- 33
- Cu-SchichtCu layer
- 44
- Umverdrahtungrewiring
- 4'4 '
- Umverdrahtungrewiring
- 55
- Resistmaskeresist mask
- 66
- Opferschichtsacrificial layer
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE200410023752 DE102004023752B4 (en) | 2004-05-11 | 2004-05-11 | Method for avoiding the reduction of the thickness of the rewiring |
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DE200410023752 DE102004023752B4 (en) | 2004-05-11 | 2004-05-11 | Method for avoiding the reduction of the thickness of the rewiring |
Publications (2)
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DE102004023752A1 DE102004023752A1 (en) | 2005-12-15 |
DE102004023752B4 true DE102004023752B4 (en) | 2006-08-24 |
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ID=35404208
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CN109119343A (en) * | 2017-06-22 | 2019-01-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4810332A (en) * | 1988-07-21 | 1989-03-07 | Microelectronics And Computer Technology Corporation | Method of making an electrical multilayer copper interconnect |
EP0382080A2 (en) * | 1989-02-09 | 1990-08-16 | National Semiconductor Corporation | Bump structure for reflow bonding of IC devices |
EP0541436B1 (en) * | 1991-11-06 | 1998-02-11 | Fujitsu Limited | Conductive pattern layer structure and method of producing the conductive pattern layer structure |
-
2004
- 2004-05-11 DE DE200410023752 patent/DE102004023752B4/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4810332A (en) * | 1988-07-21 | 1989-03-07 | Microelectronics And Computer Technology Corporation | Method of making an electrical multilayer copper interconnect |
EP0382080A2 (en) * | 1989-02-09 | 1990-08-16 | National Semiconductor Corporation | Bump structure for reflow bonding of IC devices |
EP0541436B1 (en) * | 1991-11-06 | 1998-02-11 | Fujitsu Limited | Conductive pattern layer structure and method of producing the conductive pattern layer structure |
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