DE10196082T1 - FLIP-CHIP-Montageverfahren - Google Patents

FLIP-CHIP-Montageverfahren

Info

Publication number
DE10196082T1
DE10196082T1 DE10196082T DE10196082T DE10196082T1 DE 10196082 T1 DE10196082 T1 DE 10196082T1 DE 10196082 T DE10196082 T DE 10196082T DE 10196082 T DE10196082 T DE 10196082T DE 10196082 T1 DE10196082 T1 DE 10196082T1
Authority
DE
Germany
Prior art keywords
flip
chip
assembly process
assembly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10196082T
Other languages
English (en)
Other versions
DE10196082B4 (de
Inventor
Osamu Suzuki
Haruyuki Yoshii
Kenichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Namics Corp
Original Assignee
Namics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Namics Corp filed Critical Namics Corp
Publication of DE10196082T1 publication Critical patent/DE10196082T1/de
Application granted granted Critical
Publication of DE10196082B4 publication Critical patent/DE10196082B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
DE10196082T 2000-04-14 2001-04-13 FLIP-CHIP-Montageverfahren Expired - Fee Related DE10196082B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000-113081 2000-04-14
JP2000113081A JP2002313841A (ja) 2000-04-14 2000-04-14 フリップチップ実装方法
PCT/JP2001/003183 WO2001080302A1 (en) 2000-04-14 2001-04-13 Flip chip mounting method

Publications (2)

Publication Number Publication Date
DE10196082T1 true DE10196082T1 (de) 2003-03-13
DE10196082B4 DE10196082B4 (de) 2007-06-14

Family

ID=18625119

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10196082T Expired - Fee Related DE10196082B4 (de) 2000-04-14 2001-04-13 FLIP-CHIP-Montageverfahren

Country Status (4)

Country Link
US (1) US6841415B2 (de)
JP (1) JP2002313841A (de)
DE (1) DE10196082B4 (de)
WO (1) WO2001080302A1 (de)

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* Cited by examiner, † Cited by third party
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US7470564B2 (en) * 2002-10-28 2008-12-30 Intel Corporation Flip-chip system and method of making same
WO2004088737A1 (ja) * 2003-03-28 2004-10-14 Nippon Steel Chemical Co. Ltd. 電子装置の製造方法
TW594955B (en) * 2003-06-30 2004-06-21 Advanced Semiconductor Eng Flip chip package process
JP4514418B2 (ja) * 2003-07-24 2010-07-28 株式会社Ａｄｅｋａ ビニルエーテル硬化性組成物
JP2008177350A (ja) * 2007-01-18 2008-07-31 Fujitsu Ltd 電子装置の製造方法および製造装置
JP2008274080A (ja) * 2007-04-27 2008-11-13 Shin Etsu Chem Co Ltd 液状エポキシ樹脂組成物及び半導体装置
JP2009252869A (ja) * 2008-04-03 2009-10-29 Nec Electronics Corp 半導体装置の製造方法およびこの方法により製造された半導体装置
JP5329150B2 (ja) * 2008-08-12 2013-10-30 キヤノンマシナリー株式会社 ダイボンダ
WO2010070806A1 (ja) * 2008-12-16 2010-06-24 パナソニック株式会社 半導体装置とフリップチップ実装方法およびフリップチップ実装装置
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JP2002313841A (ja) 2002-10-25

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