CN87100892A - 在单指令多数据流并行处理机阵列中模拟附加处理机的方法 - Google Patents
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Abstract
本发明是在单指令多数据流计算机中模拟附加处理机的方法,把与每一处理机相联系的存储器划分为一组子存储器,连续地对每一个子存储器进行操作,与另一个单独的处理机相联系。这样,第一条指令或第一组指令提供给阵列的所有处理机,使得至少一部分处理机处理存储在第一子存储器的第一个或第一组存储单元中的数据,同样的第一条指令或第一组指令提供给阵列的所有处理机,使得至少一部分处理机处理存储在第二子存储器的同样的第一个存储单元中的数据,用这种方式操作单指令多数据流计算机,改变阵列中的处理机的数目,按照问题需要提供处理机的数量。
Description
本发明涉及一种在单指令多数据流并行处理机阵列中模拟附加处理机的方法。
在单指令多数据流计算机中,大量的处理机并行处理一项算题,在Connection Machine(注册商标)计算机中,并行联接着32000多个处理机/存储器的单指令多数据流处理机阵列。虽然大量处理机/存储器的出现代表着技术的高度进展,但仍然需要具有更多处理机/存储器的阵列。例如,在显示时,如果能够为显示中每一个象素的数据点提供一个处理机/存储器,那就十分有益了。为了实现具有这种能力的1000×1000个象素的高分辨率显示,就必须提供1,000,000个处理机/存储器。在模拟视觉和其它涉及人工智能研究的装置中,也需要类似的数量。其它方面的应用,例如在“模拟由偏微分方程描述的***的方法和设备”中叙述的流体介质的各种模拟方法,如果这些发明要能够达到实际可用的话,也需要大量的处理机/存储器。
我们发现,在单指令多数据流计算机中可以这样来模拟附加的处理机,即把与每一个处理机相联系的存储器划分为一组子存储器,然后连续地对每一个子存储器进行操作,就好象它是与另一个单独的处理机相联系。这样,第一条指令或第一组指令提供给阵列的所有处理机,使得至少一部分处理机处理存储在第一子存储器的第一个或第一组存储单元中的数据,然后,同样的第一条指令或第一组指令提供给阵列的所有处理机,使得至少一部分处理机处理存储在第二子存储器的同样的第一个存储单元中的数据,以后,对每一个子存储器都是类似地继续下去。
用这种方式操作单指令多数据流计算机,就有可能实际上改变阵列中的处理机的数目,按照问题的需要提供处理机的数量。这就允许各种需要大量处理机的程序在那些并不实际具有那么多的处理机的计算机上运行。这样就有可能对本来要用别的办法才能实现运算的问题,例如,对产生具有高分辨率的显示的问题进行运算。
在模拟偏微分方程所描述的***的情形下,本发明所提供的技术使得在一个仅用32,768个处理机的阵列中计算4,000,000个点以上的数据成为可能。
本发明的上述和其它目的、特点以及优点将由于下面对本发明的最佳实施例的详细叙述而更容易了解,在这一实施例中:
图1和图2简略地画出了本发明的实施中优先采用的一种单指令多数据流处理机的各个部分。
图3是说明本发明实施的流程图。
本发明主要用于单指令多数据流计算机,例如用于申请号为499,474的美国专利申请中详细描述的Connection Machine计算机。
图1重新画出了上述申请中的图1A,图中,这一计算机***包括一个计算机主机10,一个微控制器20,一个并行处理集成电路35的阵列30,一个数据发送器(数据源)40,一个第一缓冲器和多路转换器/多路分配器50,第一、第二、第三和第四双向总线控制电路60、65、70和75,一个第二缓冲器和多路转换器/多路分配器80,以及一个数据接收器90。计算机主机10可以是一个编程的、市场上可以购得的通用计算机,例如由数字设备公司(Digital Equipment Corp)制造的VAX(商标)计算机。微控制器20是常规设计的指令序列发生器,用来产生一系列的指令,并利用一条32位的并行总线22传送到阵列30。微控制器20在线26上接收来自阵列30的信号,这一信号是一个通用或全局信号,可以用于数据输出和状态信息。总线22和线26并行连接到每一个集成电路35,因此,来自微控制器20的信号同时加到阵列30中的每一个集成电路35,在线26上提供给微控制器20的信号由这一阵列的所有集成电路35的信号输出结合而成。
在实施本发明中所采用的Connection Machine计算机的实施例中,阵列30包括4096(=2″)个同样的集成电路35,每一个集成电路35包括16(=24)个同样的处理机/存储器36,这样,整个阵列30包括65,536(=215)个同样的处理机/存储器36。
处理机/存储器36以两种几何结构安排和互联,一种是常规的两维网格图形,处理机/存储器安排成128×512的处理机/存储器矩形阵列,并且连接到阵列中四个最邻近的单元,另一种是十五维的布尔体。
为了把每一个处理机/存储器连接到它的四个最邻近的单元,单个处理机/存储器由网格每一行和每一列上相邻的处理机/存储器之间的电气导线相连接,如上述专利申请499,474的图6A和7A所示。除了那些位于阵列边缘的集成电路以外,一个集成电路的四个最邻近的单元将被看作是在东、南、西、北与该集成电路直接相邻的四个集成电路。
在布尔体中,每一个处理机/存储器连接到十五个最邻近的单元是通过电气导线和发送程序来实现的,接线的具体方法在上面参见的专利申请740,943中已经提出,发送程序则请参见专利申请499,474。
图2与专利申请499,474中的图7A相同,详尽地揭示了作为举例说明的处理机/存储器36。如图2所示,处理机/存储器包括随机存取存储器(RAM)250,算术逻辑单元(ALU)280和标志控制器290。算术逻辑单元对来自三个数据发送器、随机存取存储器中的两个寄存器的数据和一个标志输入进行操作,产生两个输出,一个“和”输出写入随机存取存储器的一个寄存器中,一个进位输出则提供给标志控制器中的某些寄存器以及某些别的处理机/存储器。
随机存取存储器250的输入是总线152、154、156、158,来自算术逻辑单元270的“和”输出线285,来自专利申请499,474图6B中通讯接口单元(CIU)180的信息包输入线122,以及来自标志控制器290的写启动线298。随机存取存储器250的输出是线256、257。线256、257上的信号从随机存储器250同一列上两个不同的寄存器中得到,一个指定为寄存器A,另一个是寄存器B。总线152、154、156、158按照来自微控制器20的指令字访问这些寄存器和其中的列,作为说明的例子,随机存取存储器250的存储容量为4096位。
标志控制器290是具有八个一位D触发器292、一个16-2选择器294和若干逻辑门的阵列。触发器292的输入是来自算术逻辑单元280的进位输出信号,线298上来自选择器294的写启动信号,以及来自专利申请499,474的图6B中可编程逻辑阵列(PLA)150的总线172的八条线。线172是地址线,其中每一条连接到一个不同的触发器292以选择标志位所要写入的触发器,触发器292的输出则提供给选择器294。
选择器294的输入端连接到16条标志信号线295,其中8条来自触发器292,选择器294的输入端还连接到总线174、176每一条的16根线,线174和176也是地址线,选择一条标志信号线,作为输出或进一步处理,当哪一个标志被对应的地址线174和176所选出时,选择器294就在线296和297上产生输出,在专利申请499,474的表Ⅳ中详细定义了这些标志。
算术逻辑单元280包括一个1-8译码器282,一个“和”输出选择器284和一个进位输出选择器286。如在专利申请499,474中详细描述过的那样,这使得它能够产生用于许多功能,包括加、逻辑或和逻辑与的“和”输出以及进位输出。算术逻辑单元280一次处理3位,两个在线256、257上,来自随机存取存储器250的寄存器A和B,一个在线296上,来自标志控制器290。算术逻辑单元有两个输出:一个是线285上的“和”输出,它被写入随机存取存储器250的寄存器A,一个是线287上的进位输出,它被写入标志寄存器292,并传送到与该处理机/存储器相连的另一处理机/存储器36的东、南、西、北和菊花链输入端。
按照本发明,每一个处理机/存储器可以被分为功能相同的几个单元,事实上,每一单元就象一个独立的处理机/存储器那样工作,共享一个实际的处理机/存储器的随机存取存储器、算术逻辑单元和标志控制器。在一个实际的处理机/存储器中可以分成多少个这种单元取决于每一单元对存储器的需要量。
把一个实际的处理机/存储器划分为几个部分(单元)是通过下列方式来完成的,以同一方法将每一个实际的处理机/存储器的存储器分区,并赋予图1中的微控制器20以一定的能力,使其控制每一个实际的处理机/存储器首先在分区的存储器的一段区域上操作,然后在下一段区域上操作,等等,依此类推,在存储器的每一子区间上进行操作。说明这一过程的流程图画在图3中。
存储器的划分很容易完成,例如,在这一例子中的Connection Machine计算机,每一个随机存取存储器250包含4096位或512个8位字节,图中作为例子,每字节具有一个单独的存储单元或地址,从000至511,要把存储器划分为四个子存储器,只须把000至127的存储单元指定为第一子存储器,128至255的存储单元指定为第二子存储器,256至383的存储单元指定为第三子存储器,以及把384至511的存储单元指定为第四子存储器。如果需要的话,存储器还可以分成更小的子区间。
在每一个子存储器中,与第一个存储单元具有同样对应关系的存储单元都以同样方式使用。例如,如果一个表示角度大小的度、分、秒的数据存储在第一子存储器的第一、第二和第三存储单元000、001和002中,那末给出一个角度的度、分、秒的数据也存储在第二子存储器的第一、第二和第三个存储单元128、129和130中,存储在第三子存储器的第一、第二和第三个存储单元256、257和258中,存储在第四子存储器的第一、第二和第三个存储单元384、385和386中。
无论它涉及的是一个或多个运算操作,在每一段分区的存储器上所执行的操作序列总是相同的,从分区的存储器的一段向下一段进行的能力可以用不同的方法获得。例如,控制器给出的程序中所有寻址可以参照每一个子存储单元的第一存储地址来进行,或者,程序中使用的存储地址可以用程序中的对应项来给出,当从分区的存储器的一段进行到下一段时,这些地址可以加1(进行增量)。
显然,对于掌握了本发明的人来说,在上面所描述的发明的范围内可以作出许多种不同变化。
Claims (3)
1、一种单指令多数据流并行处理机,包括一个控制器,一个由所述的控制器并行控制的处理机阵列,每一个处理机具有一个同样的输入端、一个同样的输出端、一个同样的处理单元和一个与每个处理单元相连的同样的存储器,处理单元按照所述的控制器提供的指令对其输入端和与其相连的存储器所提供的数据进行操作,并在其输出端产生数据,一种模拟阵列中存在附加的处理机的方法包括步骤:
a,以同样的方式划分与处理单元相连的存储单元,形成一组与每一处理单元相连的子存储器,
b,由控制器向处理机至少提供第一条指令或第一组指令,使得至少一部分处理机的处理单元都处理存储在与处理单元相连的第一子存储器的第一存储单元内的数据,
c,在其后的一个时刻,由控制器向处理机提供所述的第一条指令或第一组指令,使得至少一部分处理机的处理单元都处理存储在与处理机相连的第二子存储器的同样的第一存储单元内的数据。
2、权利要求1所述的方法,还进一步包括对存储在第一和第二子存储器的同样的第一存储单元内的新数据重复进行步骤(b)和(c)的步骤。
3、权利要求1所述的方法,它还进一步包括对存储在第一和第二子存储器的第二存储单元内的数据重复进行步骤(b)和(c)的步骤。
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US06/832,913 US4773038A (en) | 1986-02-24 | 1986-02-24 | Method of simulating additional processors in a SIMD parallel processor array |
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1987
- 1987-02-20 CN CN198787100892A patent/CN87100892A/zh active Pending
- 1987-02-23 EP EP87301523A patent/EP0237218A3/en not_active Withdrawn
- 1987-02-24 JP JP62039301A patent/JPS62264357A/ja active Pending
Cited By (1)
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CN101095326B (zh) * | 2004-11-05 | 2013-07-24 | 辉达技术英国有限公司 | 计算编码的正交振幅调制的信号的对数似然比的方法和*** |
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EP0237218A3 (en) | 1988-04-20 |
JPS62264357A (ja) | 1987-11-17 |
EP0237218A2 (en) | 1987-09-16 |
US4773038A (en) | 1988-09-20 |
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